1996

Logic Synthesis and Verification Algorithms

Authors:

ISBN: 978-0-7923-9746-5 (Print) 978-0-306-47592-4 (Online)

Table of contents (13 chapters)

  1. Introduction

    1. No Access

      Book Chapter

      Pages 5-45

      Introduction

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      Book Chapter

      Pages 47-76

      A Quick Tour of Logic Synthesis with the Help of a Simple Example

  2. Two Level Logic Synthesis

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      Book Chapter

      Pages 77-126

      Boolean Algebras

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      Book Chapter

      Pages 127-183

      Synthesis of Two-Level Circuits

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      Book Chapter

      Pages 185-218

      Heuristic Minimization of Two-level Circuits

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      Book Chapter

      Pages 219-254

      Binary Decision Diagrams (BDDs)

  3. Models of Sequential Systems

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      Book Chapter

      Pages 255-324

      Models of Sequential Systems

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      Book Chapter

      Pages 325-368

      Synthesis and Verification of Finite State Machines

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      Book Chapter

      Pages 369-403

      Finite Automata

  4. Multilevel Logic Synthesis

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      Book Chapter

      Pages 409-453

      Multi-Level Logic Synthesis

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      Book Chapter

      Pages 455-474

      Multi-Level Minimization

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      Book Chapter

      Pages 475-503

      Automatic Test Generation for Combinational Circuits

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      Book Chapter

      Pages 505-521

      Technology Mapping