Book Volume 3164 2005

Power-Aware Computer Systems

Third International Workshop, PACS 2003, San Diego, CA, USA, December 1, 2003 Revised Papers


ISBN: 978-3-540-24031-0 (Print) 978-3-540-28641-7 (Online)

Table of contents (14 chapters)

  1. Front Matter

    Pages -

  2. Compilers

    1. Chapter

      Pages 1-12

      Runtime Biased Pointer Reuse Analysis and Its Application to Energy Efficiency

    2. Chapter

      Pages 13-25

      Inter-program Compilation for Disk Energy Reduction

  3. Embedded Systems

    1. Chapter

      Pages 26-40

      Energy Consumption in Mobile Devices: Why Future Systems Need Requirements–Aware Energy Scale-Down

    2. Chapter

      Pages 41-56

      Efficient Scratchpad Allocation Algorithms for Energy Constrained Embedded Systems

    3. Chapter

      Pages 57-72

      Online Prediction of Battery Lifetime for Embedded and Mobile Devices

    4. Chapter

      Pages 73-85

      Synchroscalar: Initial Lessons in Power-Aware Design of a Tile-Based Embedded Architecture

    5. Chapter

      Pages 86-100

      Heterogeneous Wireless Network Management

  4. Microarchitectural Techniques

    1. Chapter

      Pages 101-116

      “Look It Up” or “Do the Math”: An Energy, Area, and Timing Analysis of Instruction Reuse and Memoization

    2. Chapter

      Pages 117-131

      CPU Packing for Multiprocessor Power Reduction

    3. Chapter

      Pages 132-147

      Exploring the Potential of Architecture-Level Power Optimizations

    4. Chapter

      Pages 148-163

      Coupled Power and Thermal Simulation with Active Cooling

  5. Cache and Memory Systems

    1. Chapter

      Pages 164-179

      The Synergy Between Power-Aware Memory Systems and Processor Voltage Scaling

    2. Chapter

      Pages 180-195

      Hot-and-Cold: Using Criticality in the Design of Energy-Efficient Caches

    3. Chapter

      Pages 196-214

      PARROT: Power Awareness Through Selective Dynamically Optimized Traces

  6. Back Matter

    Pages -