VLSI 2010 Annual Symposium

Selected papers

ISBN: 978-94-007-1487-8 (Print) 978-94-007-1488-5 (Online)

Table of contents (20 chapters)

  1. Front Matter

    Pages i-x

  2. Architecture - Level Design Solutions

    1. Front Matter

      Pages 1-1

    2. No Access

      Book Chapter

      Pages 3-16

      Intelligent NOC Hotspot Prediction

    3. No Access

      Book Chapter

      Pages 17-30

      Accurate Asynchronous Network-on-Chip Simulation Based on a Delay-Aware Model

    4. No Access

      Book Chapter

      Pages 31-45

      Trust Management Through Hardware Means: Design Concerns and Optimizations

    5. No Access

      Book Chapter

      Pages 47-63

      MULTICUBE: Multi-Objective Design Space Exploration of Multi-Core Architectures

    6. No Access

      Book Chapter

      Pages 65-79

      2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-Core Architectures

  3. Embedded System Design

    1. Front Matter

      Pages 81-81

    2. No Access

      Book Chapter

      Pages 83-115

      Adaptive Task Migration Policies for Thermal Control in MPSoCs

    3. No Access

      Book Chapter

      Pages 117-131

      A High Level Synthesis Exploration Framework with Iterative Design Space Partitioning

    4. No Access

      Book Chapter

      Pages 133-149

      A Scalable Bandwidth-Aware Architecture for Connected Component Labeling

    5. No Access

      Book Chapter

      Pages 151-164

      The SATURN Approach to SysML-Based HW/SW Codesign

    6. No Access

      Book Chapter

      Pages 165-179

      Mapping Embedded Applications on MPSoCs: The MNEMEE Approach

    7. No Access

      Book Chapter

      Pages 181-195

      The MOSART Mapping Optimization for Multi-Core ARchiTectures

  4. Emerging Devices and Nanocomputing

    1. Front Matter

      Pages 197-197

    2. No Access

      Book Chapter

      Pages 199-216

      XMSIM: Extensible Memory Simulator for Early Memory Hierarchy Evaluation

    3. No Access

      Book Chapter

      Pages 217-230

      Self-Freeze Linear Decompressors: Test Pattern Generators for Low Power Scan Testing

    4. No Access

      Book Chapter

      Pages 231-244

      SUT-RNS Forward and Reverse Converters

    5. No Access

      Book Chapter

      Pages 245-261

      Off-Chip SDRAM Access Through Spidergon STNoC

    6. No Access

      Book Chapter

      Pages 263-285

      Digital Microfluidic Biochips: A Vision for Functional Diversity and More than Moore

  5. Reconfigurable Systems

    1. Front Matter

      Pages 287-287

    2. No Access

      Book Chapter

      Pages 289-302

      FPGA Startup Through Sequential Partial and Dynamic Reconfiguration

    3. No Access

      Book Chapter

      Pages 303-318

      Two Dimensional Dynamic Multigrained Reconfigurable Hardware

    4. No Access

      Book Chapter

      Pages 319-333

      Design for Embedded Reconfigurable Systems Using MORPHEUS Platform

    5. No Access

      Book Chapter

      Pages 335-346

      New Dimensions in Design Space and Runtime Adaptivity for Multiprocessor Systems Through Dynamic and Partial Reconfiguration: The RAMPSoC Approach