Network-on-Chip Architectures

A Holistic Design Exploration

ISBN: 978-90-481-3030-6 (Print) 978-90-481-3031-3 (Online)

Table of contents (11 chapters)

  1. Front Matter

    Pages i-xxi

  2. MICRO-Architectural Exploration

    1. Front Matter

      Pages 18-18

    2. No Access

      Book Chapter

      Pages 1-12

      Introduction

    3. No Access

      Book Chapter

      Pages 13-16

      A Baseline NoC Architecture

    4. No Access

      Book Chapter

      Pages 19-40

      ViChaR: A Dynamic Virtual Channel Regulator for NoC Routers [39]

    5. No Access

      Book Chapter

      Pages 41-64

      RoCo: The Row–Column Decoupled Router – A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks [40]

    6. No Access

      Book Chapter

      Pages 65-92

      Exploring FaultoTolerant Network-on-Chip Architectures [37]

    7. No Access

      Book Chapter

      Pages 93-115

      On the Effects of Process Variation in Network-on-Chip Architectures [45]

  3. MACRO-Architectural Exploration

    1. Front Matter

      Pages 118-118

    2. No Access

      Book Chapter

      Pages 119-146

      The Quest for Scalable On-Chip Interconnection Networks: Bus/NoC Hybridization [15]

    3. No Access

      Book Chapter

      Pages 147-170

      Design and Management of 3D Chip Multiprocessors Using Network-In-Memory (NetInMem) [43]

    4. No Access

      Book Chapter

      Pages 171-197

      A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures [44]

    5. No Access

      Book Chapter

      Pages 199-205

      Digest of Additional NoC MACRO-Architectural Research

    6. No Access

      Book Chapter

      Pages 207-209

      Conclusions and Future Work

  4. Back Matter

    Pages 211-223