Reconfigurable Computing: Architectures, Tools and Applications

9th International Symposium, ARC 2013, Los Angeles, CA, USA, March 25-27, 2013. Proceedings

ISBN: 978-3-642-36811-0 (Print) 978-3-642-36812-7 (Online)

Table of contents (33 chapters)

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  1. Front Matter

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  2. Applications

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      Pages 1-12

      Heterogeneous Reconfigurable System for Adaptive Particle Filters in Real-Time Applications

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      Pages 13-24

      Hardware Acceleration of Genetic Sequence Alignment

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      Pages 25-36

      An FPGA Acceleration for the Kd-tree Search in Photon Mapping

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      Pages 37-46

      SEU Resilience of DES, AES and Twofish in SRAM-Based FPGA

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      Pages 47-58

      A Fast Poisson Solver for Hybrid Reconfigurable System

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      Pages 59-71

      An Architecture for IPv6 Lookup Using Parallel Index Generation Units

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      Pages 72-83

      Hardware Index to Set Partition Converter

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      Pages 84-89

      Teaching SoC Using Video Games to Improve Student Engagement

  3. Arithmetic

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      Pages 90-102

      Parameterized Design and Evaluation of Bandwidth Compressor for Floating-Point Data Streams in FPGA-Based Custom Computing

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      Pages 103-114

      Hardware Acceleration of Matrix Multiplication over Small Prime Finite Fields

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      Pages 115-121

      Flexible Design of a Modular Simultaneous Exponentiation Core for Embedded Platforms

  4. Design Optimization for FPGAs

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      Pages 122-133

      Architecture for Transparent Binary Acceleration of Loops with Memory Accesses

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      Pages 134-145

      Parametric Optimization of Reconfigurable Designs Using Machine Learning

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      Pages 146-153

      Performance Modeling of Pipelined Linear Algebra Architectures on FPGAs

  5. Architectures

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      Pages 154-166

      Fast Template-Based Heterogeneous MPSoC Synthesis on FPGA

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      Pages 167-178

      Configurable Fault-Tolerance for a Configurable VLIW Processor

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      Pages 179-184

      Hierarchical and Multiple Switching NoC with Floorplan Based Adaptability

  6. Place and Routing

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      Pages 185-196

      HTR: On-Chip Hardware Task Relocation for Partially Reconfigurable FPGAs

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      Pages 197-209

      Performance Analysis and Optimization of High Density Tree-Based 3D Multilevel FPGA

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      Pages 210-217

      Iterative Routing Algorithm of Inter-FPGA Signals for Multi-FPGA Prototyping Platform

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