Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

22nd International Workshop, PATMOS 2012, Newcastle upon Tyne, UK, September 4-6, 2012, Revised Selected Papers

Editors:

ISBN: 978-3-642-36156-2 (Print) 978-3-642-36157-9 (Online)

Table of contents (25 chapters)

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  1. Front Matter

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    Pages 1-10

    Sleep-Transistor Based Power-Gating Tradeoff Analyses

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    Pages 11-20

    Modelling and Analysis of Manufacturing Variability Effects from Process to Architectural Level

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    Pages 21-31

    Non-invasive Power Simulation at System-Level with SystemC

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    Pages 32-41

    A Standard Cell Optimization Method for Near-Threshold Voltage Operations

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    Pages 42-51

    An Extended Metastability Simulation Method for Synchronizer Characterization

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    Pages 52-61

    Phase Space Based NBTI Model

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    Pages 62-71

    Fast Propagation of Hamming and Signal Distances for Register-Transfer Level Datapaths

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    Pages 72-82

    Noise Margin Based Library Optimization Considering Variability in Sub-threshold

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    Pages 83-92

    TCP Window Based DVFS for Low Power Network Controller SoC

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    Pages 93-102

    Adaptive Synchronization for DVFS Applications

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    Pages 103-112

    Muller C-Element Metastability Containment

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    Pages 113-120

    Low Power Implementation of Trivium Stream Cipher

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    Pages 121-130

    A Generic Architecture for Robust Asynchronous Communication Links

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    Pages 131-141

    Direct Statistical Simulation of Timing Properties in Sequential Circuits

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    Pages 142-154

    PVTA Tolerant Self-adaptive Clock Generation Architecture

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    Pages 155-165

    On-Chip NBTI and PBTI Tracking through an All-Digital Aging Monitor Architecture

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    Pages 166-174

    Two-Phase MOBILE Interconnection Schemes for Ultra-Grain Pipeline Applications

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    Pages 175-184

    Design of a 150 mV Supply, 2 MIPS, 90nm CMOS, Ultra-Low-Power Microprocessor

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    Pages 185-193

    Run-Time Measurement of Harvested Energy for Autarkic Sensor Operation

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    Pages 194-204

    Low-Power Delay Sensors on FPGAs

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