Computer Engineering and Technology

16th National Conference, NCCET 2012, Shanghai, China, August 17-19, 2012, Revised Selected Papers

Editors:

ISBN: 978-3-642-35897-5 (Print) 978-3-642-35898-2 (Online)

Table of contents (27 chapters)

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  1. Front Matter

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  2. Session 1: Microprocessor and Implementation

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      Pages 1-7

      A Method of Balancing the Global Multi-mode Clock Network in Ultra-large Scale CPU

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      Pages 8-15

      Hardware Architecture for the Parallel Generation of Long-Period Random Numbers Using MT Method

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      Pages 16-26

      MGTE: A Multi-level Hybrid Verification Platform for a 16-Core Processor

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      Pages 27-37

      An Efficient Parallel SURF Algorithm for Multi-core Processor

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      Pages 38-48

      A Study of Cache Design in Stream Processor

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      Pages 49-56

      Design and Implementation of Dynamically Reconfigurable Token Coherence Protocol for Many-Core Processor

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      Pages 57-66

      Dynamic and Online Task Scheduling Algorithm Based on Virtual Compute Group in Many-Core Architecture

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      Pages 67-74

      ADL and High Performance Processor Design

  3. Session 2: Design of Integration Circuit

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      Pages 75-83

      The Design of the ROHC Header Compression Accelerator

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      Pages 84-91

      A Hardware Implementation of Nussinov RNA Folding Algorithm

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      Pages 92-101

      A Configurable Architecture for 1-D Discrete Wavelet Transform

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      Pages 102-110

      A Comparison of Folded Architectures for the Discrete Wavelet Transform

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      Pages 111-120

      A High Performance DSP System with Fault Tolerant for Space Missions

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      Pages 121-128

      The Design and Realization of Campus Information Release Platform Based on Android Framework

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      Pages 129-137

      A Word-Length Optimized Hardware Gaussian Random Number Generator Based on the Box-Muller Method

  4. Session 3: I/O Interconnect

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      Pages 138-147

      DAMQ Sharing Scheme for Two Physical Channels in High Performance Router

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      Pages 148-154

      Design and Implementation of Dynamic Reliable Virtual Channel for Network-on-Chip

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      Pages 155-162

      HCCM: A Hierarchical Cross-Connected Mesh for Network on Chip

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      Pages 163-172

      Efficient Broadcast Scheme Based on Sub-network Partition for Many-Core CMPs on Gem5 Simulator

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      Pages 173-184

      A Quick Method for Mapping Cores Onto 2D-Mesh Based Networks on Chip

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