Progress in VLSI Design and Test

16th International Symposium, VDAT 2012, Shibpur, India, July 1-4, 2012. Proceedings

ISBN: 978-3-642-31493-3 (Print) 978-3-642-31494-0 (Online)

Table of contents (54 chapters)

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  1. Front Matter

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  2. Lower Power 1

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      Pages 1-9

      An Efficient High Frequency and Low Power Analog Multiplier in Current Domain

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      Pages 10-18

      Design of Push-Pull Dynamic Leaker Circuit for a Low Power Embedded Voltage Regulator

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      Pages 19-29

      Power Modeling of Power Gated FSM and Its Low Power Realization by Simultaneous Partitioning and State Encoding Using Genetic Algorithm

  3. Analog VLSI Design I

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      Pages 30-39

      Design and Implementation of a Linear Feedback Shift Register Interleaver for Turbo Decoding

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      Pages 40-45

      Low Complexity Encoder for Crosstalk Reduction in RLC Modeled Interconnects

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      Pages 46-51

      Analog Performance Analysis of Dual-k Spacer Based Underlap FinFET

  4. Test and Verification I

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      Pages 52-58

      Implementation of Gating Technique with Modified Scan Flip-Flop for Low Power Testing of VLSI Chips

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      Pages 59-68

      Post-bond Stack Testing for 3D Stacked IC

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      Pages 69-78

      Translation Validation for PRES+ Models of Parallel Behaviours via an FSMD Equivalence Checker

  5. Design Techniques I

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      Pages 79-88

      Design of High Speed Vedic Multiplier for Decimal Number System

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      Pages 89-98

      An Efficient Test Design for CMPs Cache Coherence Realizing MESI Protocol

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      Pages 99-110

      An Efficient High Speed Implementation of Flexible Characteristic-2 Multipliers on FPGAs

  6. Algorithms and Applications I

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      Pages 111-120

      Arithmetic Algorithms for Ternary Number System

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      Pages 121-128

      SOI MEMS Based Over-Sampling Accelerometer Design with ΔΣ Output

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      Pages 129-138

      Design Optimization of a Wide Band MEMS Resonator for Efficient Energy Harvesting

  7. Lower Power II

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      Pages 139-146

      Ultra-Low Power Sub-threshold SRAM Cell Design to Improve Read Static Noise Margin

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      Pages 147-155

      Workload Driven Power Domain Partitioning

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      Pages 156-165

      Implementation of a New Offset Generator Block for the Low-Voltage, Low-Power Self Biased Threshold Voltage Extractor Circuit

  8. Analog VLSI Design II

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      Pages 166-171

      A High Speed, Low Jitter and Fast Acquisition CMOS Phase Frequency Detector for Charge Pump PLL

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      Pages 172-179

      ILP Based Approach for Input Vector Controlled (IVC) Toggle Maximization in Combinational Circuits

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