Book Volume 6917 2011

Cryptographic Hardware and Embedded Systems – CHES 2011

13th International Workshop, Nara, Japan, September 28 – October 1, 2011. Proceedings


ISBN: 978-3-642-23950-2 (Print) 978-3-642-23951-9 (Online)

Table of contents (33 chapters)

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  1. Front Matter

    Pages -

  2. FPGA Implementation

    1. Chapter

      Pages 1-16

      An Exploration of Mechanisms for Dynamic Cryptographic Instruction Set Extension

    2. Chapter

      Pages 17-32

      FPGA-Based True Random Number Generation Using Circuit Metastability with Adaptive Feedback Control

    3. Chapter

      Pages 33-48

      Generic Side-Channel Countermeasures for Reconfigurable Devices

  3. AES

    1. Chapter

      Pages 49-62

      Improved Collision-Correlation Power Analysis on First Order Protected AES

    2. Chapter

      Pages 63-78

      Higher-Order Glitches Free Implementation of the AES Using Secure Multi-party Computation Protocols

    3. Chapter

      Pages 79-94

      Protecting AES with Shamir’s Secret Sharing Scheme

    4. Chapter

      Pages 95-107

      A Fast and Provably Secure Higher-Order Masking of AES S-Box

  4. Elliptic Curve Cryptosystems

    1. Chapter

      Pages 108-123

      Software Implementation of Binary Elliptic Curves: Impact of the Carry-Less Multiplier on Scalar Multiplication

    2. Chapter

      Pages 124-142

      High-Speed High-Security Signatures

    3. Chapter

      Pages 143-159

      To Infinity and Beyond: Combined Attack on ECC Using Points of Low Order

  5. Lattices

    1. Chapter

      Pages 160-175

      Random Sampling for Short Lattice Vectors on Graphics Cards

    2. Chapter

      Pages 176-191

      Extreme Enumeration on GPU and in Clouds

    3. Chapter

      Pages 192-206

      Modulus Fault Attacks against RSA-CRT Signatures

  6. Side Channel Attacks

    1. Chapter

      Pages 207-222

      Breaking Mifare DESFire MF3ICD40: Power Analysis and Templates in the Real World

    2. Chapter

      Pages 223-239

      Information Theoretic and Security Analysis of a 65-Nanometer DDSLL AES S-Box

    3. Chapter

      Pages 240-255

      Thwarting Higher-Order Side Channel Analysis with Additive and Multiplicative Maskings

    4. Chapter

      Pages 256-272

      Extractors against Side-Channel Attacks: Weak or Strong?

  7. Invited Talk

    1. Chapter

      Pages 273-273

      Standardization Works for Security Regarding the Electromagnetic Environment

  8. Fault Attacks

    1. Chapter

      Pages 274-291

      Meet-in-the-Middle and Impossible Differential Fault Analysis on AES

    2. Chapter

      Pages 292-311

      On the Power of Fault Sensitivity Analysis and Collision Side-Channel Attacks in a Combined Setting

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