Euro-Par 2010 Parallel Processing Workshops

HeteroPar, HPCC, HiBB, CoreGrid, UCHPC, HPCF, PROPER, CCPI, VHPC, Ischia, Italy, August 31–September 3, 2010, Revised Selected Papers

ISBN: 978-3-642-21877-4 (Print) 978-3-642-21878-1 (Online)

Table of contents (85 chapters)

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  1. Front Matter

    Pages -

  2. Eighth International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms (HeteroPar’2010)

    1. Front Matter

      Pages 1-1

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      Pages 3-3

      HeteroPar’2010: Eighth International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms

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      Pages 5-12

      Accurate Emulation of CPU Performance

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      Pages 13-22

      Case Studies in Automatic GPGPU Code Generation with llc

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      Pages 23-30

      On the Evaluation of JavaSymphony for Heterogeneous Multi-core Clusters

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      Pages 31-39

      MAHEVE: An Efficient Reliable Mapping of Asynchronous Iterative Applications on Volatile and Heterogeneous Environments

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      Pages 41-50

      Dynamic Load Balancing of Parallel Computational Iterative Routines on Platforms with Memory Heterogeneity

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      Pages 51-61

      Dealing with Heterogeneity for Mapping MMOFPS in Distributed Systems

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      Pages 63-70

      Max-Plus Algebra and Discrete Event Simulation on Parallel Hierarchical Heterogeneous Platforms

  3. Forth Workshop on Highly Parallel Processing on a Chip (HPPC 2010)

    1. Front Matter

      Pages 71-71

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      Pages 73-75

      HPPC 2010: Forth Workshop on Highly Parallel Processing on a Chip

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      Pages 77-84

      The Massively Parallel Computing Model GCA

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      Pages 85-85

      “Single-chip Cloud Computer”, an IA Tera-scale Research Processor

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      Pages 87-97

      Evaluation of Low-Overhead Organizations for the Directory in Future Many-Core CMPs

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      Pages 99-107

      A Work Stealing Scheduler for Parallel Loops on Shared Cache Multicores

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      Pages 109-116

      Resource-Agnostic Programming for Many-Core Microgrids

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      Pages 117-125

      Programming Heterogeneous Multicore Systems Using Threading Building Blocks

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      Pages 127-135

      Fine-Grained Parallelization of a Vlasov-Poisson Application on GPU

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      Pages 137-144

      Highly Parallel Implementation of Harris Corner Detector on CSX SIMD Architecture

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      Pages 145-152

      Static Speculation as Post-link Optimization for the Grid Alu Processor

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      Pages 153-161

      A Multi-level Routing Scheme and Router Architecture to Support Hierarchical Routing in Large Network on Chip Platforms

  4. Workshop on High Performance Bioinformatics and Biomedicine (HiBB 2010)

    1. Front Matter

      Pages 163-163

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      Book Chapter

      Pages 165-166

      HiBB 2010: Workshop on High Performance Bioinformatics and Biomedicine

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