Transactions on High-Performance Embedded Architectures and Compilers III

Editors:

ISBN: 978-3-642-19447-4 (Print) 978-3-642-19448-1 (Online)

Table of contents (15 chapters)

  1. Front Matter

    Pages -

  2. Third International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC)

    1. Front Matter

      Pages 1-1

    2. No Access

      Book Chapter

      Pages 3-23

      Dynamic Cache Partitioning Based on the MLP of Cache Misses

    3. No Access

      Book Chapter

      Pages 24-42

      Cache Sensitive Code Arrangement for Virtual Machine

    4. No Access

      Book Chapter

      Pages 43-68

      Data Layout for Cache Performance on a Multithreaded Architecture

    5. No Access

      Book Chapter

      Pages 69-88

      Improving Branch Prediction by Considering Affectors and Affectees Correlations

  3. Eighth MEDEA Workshop (Selected Papers)

    1. Front Matter

      Pages 89-89

    2. No Access

      Book Chapter

      Pages 91-92

      Eighth MEDEA Workshop

    3. No Access

      Book Chapter

      Pages 93-114

      Exploring the Architecture of a Stream Register-Based Snoop Filter

    4. No Access

      Book Chapter

      Pages 115-134

      CROB: Implementing a Large Instruction Window through Compression

    5. No Access

      Book Chapter

      Pages 135-153

      Power-Aware Dynamic Cache Partitioning for CMPs

    6. No Access

      Book Chapter

      Pages 154-173

      A Multithreaded Multicore System for Embedded Media Processing

  4. Regular Papers

    1. Front Matter

      Pages 175-175

    2. No Access

      Book Chapter

      Pages 177-200

      Parallelization Schemes for Memory Optimization on the Cell Processor: A Case Study on the Harris Corner Detector

    3. No Access

      Book Chapter

      Pages 201-216

      Constructing Application-Specific Memory Hierarchies on FPGAs

  5. First Workshop on Programmability Issues for Multi-core Computers (MULTIPROG)

    1. Front Matter

      Pages 217-217

    2. No Access

      Book Chapter

      Pages 219-235

      autopin – Automated Optimization of Thread-to-Core Pinning on Multicore Systems

    3. No Access

      Book Chapter

      Pages 236-255

      Robust Adaptation to Available Parallelism in Transactional Memory Applications

    4. No Access

      Book Chapter

      Pages 256-274

      Efficient Partial Roll-Backing Mechanism for Transactional Memory Systems

    5. No Access

      Book Chapter

      Pages 275-299

      Software-Level Instruction-Cache Leakage Reduction Using Value-Dependence of SRAM Leakage in Nanometer Technologies

  6. Back Matter

    Pages -