Euro-Par 2010 - Parallel Processing

16th International Euro-Par Conference, Ischia, Italy, August 31 - September 3, 2010, Proceedings, Part II

Editors:

ISBN: 978-3-642-15290-0 (Print) 978-3-642-15291-7 (Online)

Table of contents (49 chapters)

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  1. Front Matter

    Pages -

  2. Topic 9: Parallel and Distributed Programming

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      Pages 1-1

      Parallel and Distributed Programming

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      Pages 2-13

      Transactional Mutex Locks

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      Pages 14-25

      Exceptions for Algorithmic Skeletons

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      Pages 26-37

      Generators-of-Generators Library with Optimization Capabilities in Fortress

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      Pages 38-50

      User Transparent Task Parallel Multimedia Content Analysis

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      Pages 51-62

      Parallel Simulation for Parameter Estimation of Optical Tissue Properties

  3. Topic 10: Parallel Numerical Algorithms

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      Pages 63-64

      Parallel Numerical Algorithms

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      Pages 65-76

      Scalability and Locality of Extrapolation Methods for Distributed-Memory Architectures

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      Pages 77-88

      CFD Parallel Simulation Using Getfem++ and Mumps

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      Pages 89-100

      Aggregation AMG for Distributed Systems Suffering from Large Message Numbers

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      Pages 101-112

      A Parallel Implementation of the Jacobi-Davidson Eigensolver and Its Application in a Plasma Turbulence Code

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      Pages 113-124

      Scheduling Parallel Eigenvalue Computations in a Quantum Chemistry Code

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      Pages 125-136

      Scalable Parallelization Strategies to Accelerate NuFFT Data Translation on Multicores

  4. Topic 11: Multicore and Manycore Programming

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      Pages 137-138

      Multicore and Manycore Programming

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      Pages 139-150

      JavaSymphony: A Programming and Execution Environment for Parallel and Distributed Many-Core Architectures

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      Pages 151-162

      Scalable Producer-Consumer Pools Based on Elimination-Diffraction Trees

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      Pages 163-174

      Productivity and Performance: Improving Consumability of Hardware Transactional Memory through a Real-World Case Study

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      Pages 175-186

      Exploiting Fine-Grained Parallelism on Cell Processors

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      Pages 187-198

      Optimized On-Chip-Pipelined Mergesort on the Cell/B.E.

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      Pages 199-210

      Near-Optimal Placement of MPI Processes on Hierarchical NUMA Architectures

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