Euro-Par 2009 – Parallel Processing Workshops

HPPC, HeteroPar, PROPER, ROIA, UNICORE, VHPC, Delft, The Netherlands, August 25-28, 2009, Revised Selected Papers

ISBN: 978-3-642-14121-8 (Print) 978-3-642-14122-5 (Online)

Table of contents (51 chapters)

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  1. Front Matter

    Pages -

  2. Third Workshop on Highly Parallel Processing on a Chip (HPPC 2009)

    1. Front Matter

      Pages 1-1

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      Pages 3-5

      HPPC 2009: 3rd Workshop on Highly Parallel Processing on a Chip

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      Pages 7-7

      The Next 25 Years of Computer Architecture?

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      Pages 8-8

      Software Development and Programming of Multi-core SoC

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      Pages 9-15

      HPPC 2009 Panel: Are Many-Core Computer Vendors on Track?

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      Pages 16-25

      Distance Constrained Mapping to Support NoC Platforms Based on Source Routing

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      Pages 26-35

      Parallel Variable-Length Encoding on GPGPUs

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      Pages 36-45

      Towards Metaprogramming for Parallel Systems on a Chip

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      Pages 46-55

      Dynamic Detection of Uniform and Affine Vectors in GPGPU Computations

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      Pages 56-65

      Automatic Calibration of Performance Models on Heterogeneous Multicore Architectures

  3. Seventh International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms (HeteroPar 2009)

    1. Front Matter

      Pages 67-67

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      Pages 69-70

      Preface

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      Pages 71-80

      Static Worksharing Strategies for Heterogeneous Computers with Unrecoverable Failures

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      Pages 81-90

      Resource Allocation for Multiple Concurrent In-network Stream-Processing Applications

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      Pages 91-101

      Distributed Data Partitioning for Heterogeneous Processors Based on Partial Estimation of Their Functional Performance Models

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      Pages 102-111

      An Efficient Weighted Bi-objective Scheduling Algorithm for Heterogeneous Systems

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      Pages 112-121

      Two-Dimensional Matrix Partitioning for Parallel Computing on Heterogeneous Processors Based on Their Functional Performance Models

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      Pages 122-131

      Accelerating S3D: A GPGPU Case Study

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      Pages 132-139

      Using Hybrid CPU-GPU Platforms to Accelerate the Computation of the Matrix Sign Function

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      Pages 140-149

      Modelling Pilot-Job Applications on Production Grids

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      Pages 150-161

      Modeling Resubmission in Unreliable Grids: The Bottom-Up Approach

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      Pages 162-171

      Reliable Parallel Programming Model for Distributed Computing Environments

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