Book Volume 5952 2010

High Performance Embedded Architectures and Compilers

5th International Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings

ISBN: 978-3-642-11514-1 (Print) 978-3-642-11515-8 (Online)

Table of contents (26 chapters)

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  1. Front Matter

    Pages -

  2. Invited Program

    1. Chapter

      Pages 1-1

      Embedded Systems as Datacenters

    2. Chapter

      Pages 2-2

      Larrabee: A Many-Core Intel Architecture for Visual Computing

  3. Architectural Support for Concurrency

    1. Chapter

      Pages 3-17

      Remote Store Programming

    2. Chapter

      Pages 18-34

      Low-Overhead, High-Speed Multi-core Barrier Synchronization

    3. Chapter

      Pages 35-49

      Improving Performance by Reducing Aborts in Hardware Transactional Memory

    4. Chapter

      Pages 50-65

      Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems

  4. Compilation and Runtime Systems

    1. Chapter

      Pages 66-80

      Split Register Allocation: Linear Complexity Without the Performance Penalty

    2. Chapter

      Pages 81-95

      Trace-Based Data Layout Optimizations for Multi-core Processors

    3. Chapter

      Pages 96-110

      Buffer Sizing for Self-timed Stream Programs on Heterogeneous Distributed Memory Multiprocessors

    4. Chapter

      Pages 111-125

      Automatically Tuning Sparse Matrix-Vector Multiplication for GPU Architectures

  5. Reconfigurable and Customized Architectures

    1. Chapter

      Pages 126-140

      Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions

    2. Chapter

      Pages 141-155

      Accelerating XML Query Matching through Custom Stack Generation on FPGAs

    3. Chapter

      Pages 156-170

      An Application-Aware Load Balancing Strategy for Network Processors

    4. Chapter

      Pages 171-185

      Memory-Aware Application Mapping on Coarse-Grained Reconfigurable Arrays

  6. Multicore Efficiency, Reliability, and Power

    1. Chapter

      Pages 186-200

      Maestro: Orchestrating Lifetime Reliability in Chip Multiprocessors

    2. Chapter

      Pages 201-215

      Combining Locality Analysis with Online Proactive Job Co-scheduling in Chip Multiprocessors

    3. Chapter

      Pages 216-231

      RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor

    4. Chapter

      Pages 232-246

      Performance and Power Aware CMP Thread Allocation Modeling

  7. Memory Organization and Optimization

    1. Chapter

      Pages 247-261

      Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matching

    2. Chapter

      Pages 262-276

      Scalable Shared-Cache Management by Containing Thrashing Workloads

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