Book Volume 5415 2009

Euro-Par 2008 Workshops - Parallel Processing

VHPC 2008, UNICORE 2008, HPPC 2008, SGS 2008, PROPER 2008, ROIA 2008, and DPA 2008, Las Palmas de Gran Canaria, Spain, August 25-26, 2008, Revised Selected Papers

ISBN: 978-3-642-00954-9 (Print) 978-3-642-00955-6 (Online)

Table of contents (50 chapters)

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  1. Front Matter

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  2. Workshop on Virtualization in High-Performance Cluster and Grid Computing (VHPC 2008)

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      Pages 1-1

      Workshop on Virtualization in High-Performance Cluster and Grid Computing (VHPC 2008)

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      Pages 3-12

      Tools and Techniques for Managing Virtual Machine Images

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      Pages 13-22

      Dynamic on Demand Virtual Clusters in Grid

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      Pages 23-32

      Dynamic Provisioning of Virtual Clusters for Grid Computing

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      Pages 33-42

      Dynamic Resources Management of Virtual Appliances on a Computational Cluster

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      Chapter

      Pages 43-52

      Complementarity between Virtualization and Single System Image Technologies

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      Chapter

      Pages 53-62

      Efficient Shared Memory Message Passing for Inter-VM Communications

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      Chapter

      Pages 63-71

      An Analysis of HPC Benchmarks in Virtual Machine Environments

  3. UNICORE Summit 2008

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      Pages 73-73

      UNICORE Summit 2008

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      Pages 75-83

      Space-Based Approach to High-Throughput Computations in UNICORE 6 Grids

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      Chapter

      Pages 84-93

      The Chemomentum Data Services – A Flexible Solution for Data Handling in UNICORE

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      Pages 94-102

      A Reliable and Fast Data Transfer for Grid Systems Using a Dynamic Firewall Configuration

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      Chapter

      Pages 103-112

      Workflow Service Extensions for UNICORE 6 – Utilising a Standard WS-BPEL Engine for Grid Service Orchestration

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      Chapter

      Pages 113-122

      Benchmarking of Integrated OGSA-BES with the Grid Middleware

  4. Second Workshop on Highly Parallel Processing on a Chip (HPPC 2008)

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      Pages 123-125

      Second Workshop on Highly Parallel Processing on a Chip (HPPC 2008)

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      Pages 127-128

      Models for Parallel and Hierarchical On-Chip Computation

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      Pages 129-130

      Building a Concurrency and Resource Allocation Model into a Processor’s ISA

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      Pages 131-140

      Optimized Pipelined Parallel Merge Sort on the Cell BE

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      Pages 141-151

      Towards an Intelligent Environment for Programming Multi-core Computing Systems

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      Chapter

      Pages 152-162

      Adaptive Read Validation in Time-Based Software Transactional Memory

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