Transactions on High-Performance Embedded Architectures and Compilers II

Editors:

ISBN: 978-3-642-00903-7 (Print) 978-3-642-00904-4 (Online)

Table of contents (16 chapters)

  1. Front Matter

    Pages -

  2. Special Section on High-Performance Embedded Architectures and Compilers

    1. Front Matter

      Pages 1-1

    2. No Access

      Book Chapter

      Pages 3-3

      Introduction

    3. No Access

      Book Chapter

      Pages 4-22

      Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches

    4. No Access

      Book Chapter

      Pages 23-44

      Compiler-Assisted Memory Encryption for Embedded Processors

    5. No Access

      Book Chapter

      Pages 45-64

      Branch Predictor Warmup for Sampled Simulation through Branch History Matching

    6. No Access

      Book Chapter

      Pages 65-84

      Data Cache Techniques to Save Power and Deliver High Performance in Embedded Systems

    7. No Access

      Book Chapter

      Pages 85-104

      Combining Edge Vector and Event Counter for Time-Dependent Power Behavior Characterization

  3. Regular Papers

    1. Front Matter

      Pages 105-105

    2. No Access

      Book Chapter

      Pages 107-127

      Accurate Instruction Pre-scheduling in Dynamically Scheduled Processors

    3. No Access

      Book Chapter

      Pages 128-148

      Fetch Gating Control through Speculative Instruction Window Weighting

    4. No Access

      Book Chapter

      Pages 149-172

      Fast Code Generation for Embedded Processors with Aliased Heterogeneous Registers

    5. No Access

      Book Chapter

      Pages 173-200

      Linux Kernel Compaction through Cold Code Swapping

    6. No Access

      Book Chapter

      Pages 201-221

      Complexity Effective Bypass Networks

    7. No Access

      Book Chapter

      Pages 222-241

      A Context-Parameterized Model for Static Analysis of Execution Times

    8. No Access

      Book Chapter

      Pages 242-268

      Reexecution and Selective Reuse in Checkpoint Processors

    9. No Access

      Book Chapter

      Pages 269-285

      Compiler Support for Code Size Reduction Using a Queue-Based Processor

    10. No Access

      Book Chapter

      Pages 286-306

      Power-Aware Bus Coscheduling for Periodic Realtime Applications Running on Multiprocessor SoC

    11. No Access

      Book Chapter

      Pages 307-325

      Performance Characterization for the Implementation of Content Addressable Memories Based on Parallel Hashing Memories

  4. Back Matter

    Pages -