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High Performance Embedded Architectures and Compilers

Fourth International Conference, HiPEAC 2009

  • Conference proceedings
  • © 2009

Overview

Editors:
  1. André Seznec

    1. IRISA, Campus de Beaulieu, Rennes Cedex, France

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  2. Joel Emer

    1. Intel Corporation, Massachusetts Microprocessor Design Center, Hudson, USA

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  3. Michael O’Boyle

    1. School of Informatics, Institute for Computing Systems Architecture, Edinburgh, United Kingdom

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  4. Margaret Martonosi

    1. Department of Electrical Engineering, Princeton University, Princeton, USA

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  5. Theo Ungerer

    1. Department of Computer Science, University of Augsburg, Augsburg, Germany

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Part of the book series: Lecture Notes in Computer Science (LNCS, volume 5409)

Part of the book sub series: Theoretical Computer Science and General Issues (LNTCS)

Included in the following conference series:

Conference proceedings info: HiPEAC 2009.

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Table of contents (29 papers)

  1. Front Matter

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  2. Invited Program

    1. Keynote: Challenges on the Road to Exascale Computing

      • Tilak Agerwala
      Pages 1-1

    2. Keynote: Compilers in the Manycore Era

      • François Bodin
      Pages 2-3

  3. I Dynamic Translation and Optimisation

    1. Steal-on-Abort: Improving Transactional Memory Performance through Dynamic Transaction Reordering

      • Mohammad Ansari, Mikel Luján, Christos Kotselidis, Kim Jarvis, Chris Kirkham, Ian Watson
      Pages 4-18

    2. Predictive Runtime Code Scheduling for Heterogeneous Architectures

      • Víctor J. Jiménez, Lluís Vilanova, Isaac Gelado, Marisa Gil, Grigori Fursin, Nacho Navarro
      Pages 19-33

    3. Collective Optimization

      • Grigori Fursin, Olivier Temam
      Pages 34-49

    4. High Speed CPU Simulation Using LTU Dynamic Binary Translation

      • Daniel Jones, Nigel Topham
      Pages 50-64

  4. II Low Level Scheduling

    1. Integrated Modulo Scheduling for Clustered VLIW Architectures

      • Mattias V. Eriksson, Christoph W. Kessler
      Pages 65-79

    2. Software Pipelining in Nested Loops with Prolog-Epilog Merging

      • Mohammed Fellahi, Albert Cohen
      Pages 80-94

    3. A Flexible Code Compression Scheme Using Partitioned Look-Up Tables

      • Martin Thuresson, Magnus Själander, Per Stenstrom
      Pages 95-109

  5. III Parallelism and Resource Control

    1. MLP-Aware Runahead Threads in a Simultaneous Multithreading Processor

      • Kenzo Van Craeynest, Stijn Eyerman, Lieven Eeckhout
      Pages 110-124

    2. IPC Control for Multiple Real-Time Threads on an In-Order SMT Processor

      • Jörg Mische, Sascha Uhrig, Florian Kluge, Theo Ungerer
      Pages 125-139

    3. A Hardware Task Scheduler for Embedded Video Processing

      • Ghiath Al-Kadi, Andrei Sergeevich Terechko
      Pages 140-152

    4. Finding Stress Patterns in Microprocessor Workloads

      • Frederik Vandeputte, Lieven Eeckhout
      Pages 153-167

  6. IV Communication

    1. Deriving Efficient Data Movement from Decoupled Access/Execute Specifications

      • Lee W. Howes, Anton Lokhmotov, Alastair F. Donaldson, Paul H. J. Kelly
      Pages 168-182

    2. MPSoC Design Using Application-Specific Architecturally Visible Communication

      • Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne
      Pages 183-197

    3. Communication Based Proactive Link Power Management

      • Sai Prashanth Muralidhara, Mahmut Kandemir
      Pages 198-215

  7. V Mapping for CMPs

    1. Mapping and Synchronizing Streaming Applications on Cell Processors

      • Maik Nijhuis, Herbert Bos, Henri E. Bal, Cédric Augonnet
      Pages 216-230

    2. Adapting Application Mapping to Systematic Within-Die Process Variations on Chip Multiprocessors

      • Yang Ding, Mahmut Kandemir, Mary Jane Irwin, Padma Raghavan
      Pages 231-247

    3. Accomodating Diversity in CMPs with Heterogeneous Frequencies

      • Major Bhadauria, Vince Weaver, Sally A. McKee
      Pages 248-262
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About this book

This book constitutes the refereed proceedings of the Fourth International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2009, held in Paphos, Cyprus, in January 2009. The 27 revised full papers presented together with 2 invited keynote paper were carefully reviewed and selected from 97 submissions. The papers are organized in topical sections on dynamic translation and optimisation, low level scheduling, parallelism and resource control, communication, mapping for CMPs, power, cache issues as well as parallel embedded applications.

Editors and Affiliations

  • IRISA, Campus de Beaulieu, Rennes Cedex, France

    André Seznec

  • Intel Corporation, Massachusetts Microprocessor Design Center, Hudson, USA

    Joel Emer

  • School of Informatics, Institute for Computing Systems Architecture, Edinburgh, United Kingdom

    Michael O’Boyle

  • Department of Electrical Engineering, Princeton University, Princeton, USA

    Margaret Martonosi

  • Department of Computer Science, University of Augsburg, Augsburg, Germany

    Theo Ungerer

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