Languages and Compilers for Parallel Computing

20th International Workshop, LCPC 2007, Urbana, IL, USA, October 11-13, 2007, Revised Selected Papers

Editors:

ISBN: 978-3-540-85260-5 (Print) 978-3-540-85261-2 (Online)

Table of contents (23 chapters)

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  1. Front Matter

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  2. Reliability

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      Book Chapter

      Pages 1-15

      Compiler-Enhanced Incremental Checkpointing

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      Book Chapter

      Pages 16-31

      Techniques for Efficient Software Checking

  3. Languages

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      Book Chapter

      Pages 32-46

      Revisiting SIMD Programming

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      Pages 47-62

      Multidimensional Blocking in UPC

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      Pages 63-77

      An Experimental Evaluation of the New OpenMP Tasking Model

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      Book Chapter

      Pages 78-94

      Language Extensions in Support of Compiler Parallelization

  4. Parallel Compiler Technology I

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      Pages 95-109

      Concurrency Analysis for Shared Memory Programs with Textually Unaligned Barriers

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      Pages 110-124

      Iteration Disambiguation for Parallelism Identification in Time-Sliced Applications

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      Pages 125-140

      A Novel Asynchronous Software Cache Implementation for the Cell-BE Processor

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      Book Chapter

      Pages 141-155

      Pillar: A Parallel Implementation Language

    5. Libraries

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        Book Chapter

        Pages 156-171

        Associative Parallel Containers in STAPL

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        Pages 172-186

        Explicit Dependence Metadata in an Active Visual Effects Library

      Run-Time Systems and Performance Analysis

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        Book Chapter

        Pages 187-201

        Supporting Huge Address Spaces in a Virtual Machine for Java on a Cluster

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        Pages 202-216

        Modeling Relations between Inputs and Dynamic Behavior for General Programs

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        Pages 217-231

        Evaluation of RDMA Opportunities in an Object-Oriented DSM

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        Book Chapter

        Pages 232-245

        Automatic Communication Performance Debugging in PGAS Languages

  5. Parallel Compiler Technology II

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      Book Chapter

      Pages 246-260

      Exploiting SIMD Parallelism with the CGiS Compiler Framework

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      Book Chapter

      Pages 261-275

      Critical Block Scheduling: A Thread-Level Parallelizing Mechanism for a Heterogeneous Chip Multiprocessor Architecture

  6. Languages II

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      Book Chapter

      Pages 276-291

      Capsules: Expressing Composable Computations in a Parallel Programming Model

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      Book Chapter

      Pages 292-307

      Communicating Multiprocessor-Tasks

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