Transactions on High-Performance Embedded Architectures and Compilers I

Editors:

ISBN: 978-3-540-71527-6 (Print) 978-3-540-71528-3 (Online)

Table of contents (21 chapters)

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  1. Front Matter

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  2. High Performance Processor Chips

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      Pages 1-4

      High Performance Processor Chips

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      Pages 5-29

      High-Performance Embedded Architecture and Compilation Roadmap

  3. Part 1: First International Conference on High-Performance Embedded Architectures and Compilers, HiPEAC 2005. Best Papers

    1. Front Matter

      Pages 31-31

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      Pages 33-33

      Introduction to Part 1

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      Pages 34-53

      Quick and Practical Run-Time Evaluation of Multiple Program Optimizations

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      Pages 54-73

      Specializing Cache Structures for High Performance and Energy Conservation in Embedded Systems

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      Pages 74-94

      GCH: Hints for Triggering Garbage Collections

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      Pages 95-115

      Memory-Centric Security Architecture

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      Pages 116-135

      Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems

  4. Part 2: Optimizing Compilers

    1. Front Matter

      Pages 137-137

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      Pages 139-139

      Introduction to Part 2

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      Pages 140-158

      Convergent Compilation Applied to Loop Unrolling

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      Pages 159-178

      Finding and Applying Loop Transformations for Generating Optimized FPGA Implementations

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      Pages 179-193

      Dynamic and On-Line Design Space Exploration for Reconfigurable Architectures

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      Pages 194-213

      Automatic Discovery of Coarse-Grained Parallelism in Media Applications

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      Pages 214-233

      An Approach for Enhancing Inter-processor Data Locality on Chip Multiprocessors

  5. Part 3: ACM International Conference on Computing Frontiers 2006. Best Papers

    1. Front Matter

      Pages 235-235

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      Pages 237-238

      Introduction to Part 3

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      Pages 239-258

      Hardware/Software Architecture for Real-Time ECG Monitoring and Analysis Leveraging MPSoC Technology

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      Pages 259-278

      Using Application Bisection Bandwidth to Guide Tile Size Selection for the Synchroscalar Tile-Based Architecture

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      Pages 279-297

      Static Cache Partitioning Robustness Analysis for Embedded On-Chip Multi-processors

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      Pages 298-316

      Selective Code Compression Scheme for Embedded Systems

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      Pages 317-340

      A Prefetching Algorithm for Multi-speed Disks

  6. Back Matter

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