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  • Conference proceedings
  • © 2007

Transactions on High-Performance Embedded Architectures and Compilers I

Editors:

  1. Per Stenström

    1. Department of Computer Science and Engineering, Chalmers University of Technology, Gothenburg, Sweden

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Part of the book series: Lecture Notes in Computer Science (LNCS, volume 4050)

Part of the book sub series: Transactions on High-Performance Embedded Architectures and Compilers (THIPEAC)

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Table of contents (21 papers)

  1. Front Matter

    PDF

  2. High Performance Processor Chips

    1. High Performance Processor Chips

      • Maurice V. Wilkes
      Pages 1-4

    2. High-Performance Embedded Architecture and Compilation Roadmap

      • Koen De Bosschere, Wayne Luk, Xavier Martorell, Nacho Navarro, Mike O’Boyle, Dionisios Pnevmatikatos et al.
      Pages 5-29

  3. Part 1: First International Conference on High-Performance Embedded Architectures and Compilers, HiPEAC 2005. Best Papers

    1. Front Matter

      Pages 31-31
      PDF

    2. Introduction to Part 1

      • Per Stenström
      Pages 33-33

    3. Quick and Practical Run-Time Evaluation of Multiple Program Optimizations

      • Grigori Fursin, Albert Cohen, Michael O’Boyle, Olivier Temam
      Pages 34-53

    4. Specializing Cache Structures for High Performance and Energy Conservation in Embedded Systems

      • Michael J. Geiger, Sally A. McKee, Gary S. Tyson
      Pages 54-73

    5. GCH: Hints for Triggering Garbage Collections

      • Dries Buytaert, Kris Venstermans, Lieven Eeckhout, Koen De Bosschere
      Pages 74-94

    6. Memory-Centric Security Architecture

      • Weidong Shi, Chenghuai Lu, Hsien-Hsin S. Lee
      Pages 95-115

  4. Part 2: Optimizing Compilers

    1. Front Matter

      Pages 137-137
      PDF

    2. Introduction to Part 2

      • Mike O’Boyle, François Bodin, Marcelo Cintra
      Pages 139-139

    3. Convergent Compilation Applied to Loop Unrolling

      • Nicholas Nethercote, Doug Burger, Kathryn S. McKinley
      Pages 140-158

    4. Finding and Applying Loop Transformations for Generating Optimized FPGA Implementations

      • Harald Devos, Kristof Beyls, Mark Christiaens, Jan Van Campenhout, Erik H. D’Hollander, Dirk Stroobandt
      Pages 159-178

    5. Dynamic and On-Line Design Space Exploration for Reconfigurable Architectures

      • Fakhreddine Ghaffari, Michel Auguin, Mohamed Abid, Maher Ben Jemaa
      Pages 179-193

    6. Automatic Discovery of Coarse-Grained Parallelism in Media Applications

      • Shane Ryoo, Sain-Zee Ueng, Christopher I. Rodrigues, Robert E. Kidd, Matthew I. Frank, Wen-mei W. Hwu
      Pages 194-213

  5. Part 3: ACM International Conference on Computing Frontiers 2006. Best Papers

    1. Front Matter

      Pages 235-235
      PDF

    2. Introduction to Part 3

      • Sally A. McKee
      Pages 237-238

    3. Hardware/Software Architecture for Real-Time ECG Monitoring and Analysis Leveraging MPSoC Technology

      • Iyad Al Khatib, Davide Bertozzi, Francesco Poletti, Luca Benini, Axel Jantsch, Mohamed Bechara et al.
      Pages 239-258
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Keywords

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Editors and Affiliations

  • Department of Computer Science and Engineering, Chalmers University of Technology, Gothenburg, Sweden

    Per Stenström

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Buy it now

eBook USD 39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Other ways to access

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