System Specification and Design Languages

Selected Contributions from FDL 2010

  • Tom J. Kaźmierski
  • Adam Morawiec
Conference proceedings

DOI: 10.1007/978-1-4614-1427-8

Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 106)

Table of contents (15 papers)

  1. Front Matter
    Pages i-xii
  2. Formal Hardware/Software Co-verification of Application Specific Instruction Set Processors
    Sacha Loitz, Markus Wedler, Dominik Stoffel, Christian Brehm, Wolfgang Kunz, Norbert Wehn
    Pages 1-20
  3. Evaluating Debugging Algorithms from a Qualitative Perspective
    Alexander Finder, Görschwin Fey
    Pages 21-36
  4. Mapping of Concurrent Object-Oriented Models to Extended Real-Time Task Networks
    Matthias Büker, Kim Grüttner, Philipp A. Hartmann, Ingo Stierand
    Pages 37-53
  5. A Framework for Interactive Refinement of Mixed HW/SW/Analog Systems
    Tobias Kirchner, Nico Bannow, Christian Kerstan, Christoph Grimm
    Pages 71-89
  6. Bottom-up Verification for CMOS Photonic Linear Heterogeneous System
    Bo Wang, Ian O’Connor, Emmanuel Drouard, Lioua Labrak
    Pages 91-104
  7. Towards Abstract Analysis Techniques for Range Based System Simulations
    Florian Schupfer, Michael Kärgel, Christoph Grimm, Markus Olbrich, Erich Barke
    Pages 105-121
  8. Modeling Time-Triggered Architecture Based Real-Time Systems Using SystemC
    Jon Perez, Carlos Fernando Nicolas, Roman Obermaisser, Christian El Salloum
    Pages 123-141
  9. Rapid Prototyping of Complex HW/SW Systems using a Timing and Power Aware ESL Framework
    Kim Grüttner, Kai Hylla, Sven Rosinger, Wolfgang Nebel
    Pages 157-173
  10. Towards Accurate Source-Level Annotation of Low-Level Properties Obtained from Optimized Binary Code
    Stefan Stattelmann, Alexander Viehl, Oliver Bringmann, Wolfgang Rosenstiel
    Pages 175-190
  11. Architecture Specifications in CλaSH
    Jan Kuper, Christiaan Baaij, Matthijs Kooijman, Marco Gerards
    Pages 191-206
  12. SyReC: A Programming Language for Synthesis of Reversible Circuits
    Robert Wille, Sebastian Offermann, Rolf Drechsler
    Pages 207-222
  13. Logical Time @ Work: Capturing Data Dependencies and Platform Constraints
    Calin Glitia, Julien DeAntoni, Frédéric Mallet
    Pages 223-238
  14. Formal Support for Untimed MARTE-SystemC Interoperability
    Pablo Peñil, Fernando Herrera, Eugenio Villar
    Pages 239-254

About these proceedings

Introduction

This book brings together a selection of the best papers from the thirteenth edition of the Forum on specification and Design Languages Conference (FDL), which was held in Southampton, UK in September 2010.  FDL is a well established international forum devoted to dissemination of research results, practical experiences and new ideas in the application of specification, design and verification languages to the design, modelling and verification of integrated circuits, complex hardware/software embedded systems, and mixed-technology systems.

  • Covers design verification, automatic synthesis and mechanized debug aids;
  • Includes language-based modeling and design techniques for embedded systems;
  • Covers design, modeling and verification of mixed physical domain and mixed signal systems that include significant analog parts in electrical and non-electrical domains;
  • Includes formal and semi-formal system level design methods for complex embedded systems based on the Unified Modelling Language (UML) and Model Driven Engineering (MDE).

 
 
 
 

 

 
 


 

Keywords

Automatic Synthesis Design Specification Languages Design Verification Embedded Systems FDL 2010 Integrated Circuits Mechanized Debugging Rapid Prototyping

Editors and affiliations

  • Tom J. Kaźmierski
    • 1
  • Adam Morawiec
    • 2
  1. 1.University of SouthamptonSouthamptonUnited Kingdom
  2. 2.ECSIGièresFrance

Bibliographic information

  • Copyright Information Springer Science+Business Media, LLC 2012
  • Publisher Name Springer, New York, NY
  • eBook Packages Engineering
  • Print ISBN 978-1-4614-1426-1
  • Online ISBN 978-1-4614-1427-8
  • Series Print ISSN 1876-1100
  • Series Online ISSN 1876-1119