2012

Low Power Design with High-Level Power Estimation and Power-Aware Synthesis

ISBN: 978-1-4614-0871-0 (Print) 978-1-4614-0872-7 (Online)

Table of contents (13 chapters)

  1. Front Matter

    Pages i-xxii

  2. No Access

    Book Chapter

    Pages 1-12

    Introduction

  3. No Access

    Book Chapter

    Pages 13-29

    Related Work

  4. No Access

    Book Chapter

    Pages 31-43

    Background

  5. No Access

    Book Chapter

    Pages 45-57

    Architectural Selection Using High Level Synthesis

  6. No Access

    Book Chapter

    Pages 59-70

    Statistical Regression Based Power Models

  7. No Access

    Book Chapter

    Pages 71-80

    Coprocessor Design Space Exploration Using High Level Synthesis

  8. No Access

    Book Chapter

    Pages 81-92

    Regression-Based Dynamic Power Estimation for FPGAs

  9. No Access

    Book Chapter

    Pages 93-103

    High Level Simulation Directed RTL Power Estimation

  10. No Access

    Book Chapter

    Pages 105-118

    Applying Verification Collaterals for Accurate Power Estimation

  11. No Access

    Book Chapter

    Pages 119-129

    Power Reduction Using High-Level Clock-Gating

  12. No Access

    Book Chapter

    Pages 131-141

    Model-Checking to Exploit Sequential Clock-Gating

  13. No Access

    Book Chapter

    Pages 143-156

    System Level Simulation Guided Approach for Clock-Gating

  14. No Access

    Book Chapter

    Pages 157-161

    Conclusions

  15. Back Matter

    Pages 163-170