2013

Design for High Performance, Low Power, and Reliable 3D Integrated Circuits

Authors:

ISBN: 978-1-4419-9541-4 (Print) 978-1-4419-9542-1 (Online)

Table of contents (20 chapters)

  1. Front Matter

    Pages i-xxviii

  2. High Performance and Low Power 3D IC Designs

    1. Front Matter

      Pages 1-1

    2. No Access

      Book Chapter

      Pages 3-40

      Regular Versus Irregular TSV Placement for 3D IC

    3. No Access

      Book Chapter

      Pages 41-73

      Steiner Routing for 3D IC

    4. No Access

      Book Chapter

      Pages 75-97

      Buffer Insertion for 3D IC

    5. No Access

      Book Chapter

      Pages 99-128

      Low Power Clock Routing for 3D IC

    6. No Access

      Book Chapter

      Pages 129-151

      Power Delivery Network Design for 3D IC

    7. No Access

      Book Chapter

      Pages 153-185

      3D Clock Routing for Pre-bond Testability

  3. Electrical Reliability in 3D IC Designs

    1. Front Matter

      Pages 187-187

    2. No Access

      Book Chapter

      Pages 189-203

      TSV-to-TSV Coupling Analysis and Optimization

    3. No Access

      Book Chapter

      Pages 205-229

      TSV Current Crowding and Power Integrity

    4. No Access

      Book Chapter

      Pages 231-250

      Modeling of Atomic Concentration at the Wire-to-TSV Interface

  4. Thermal Reliability in 3D IC Designs

    1. Front Matter

      Pages 251-251

    2. No Access

      Book Chapter

      Pages 253-283

      Multi-objective Architectural Floorplanning for 3D IC

    3. No Access

      Book Chapter

      Pages 285-308

      Thermal-Aware Gate-Level Placement for 3D IC

    4. No Access

      Book Chapter

      Pages 309-341

      3D IC Cooling with Micro-Fluidic Channels

  5. Mechanical Reliability in 3D IC Designs

    1. Front Matter

      Pages 343-343

    2. No Access

      Book Chapter

      Pages 345-378

      Mechanical Reliability Analysis and Optimization for 3D ICs

    3. No Access

      Book Chapter

      Pages 379-414

      Impact of Mechanical Stress on Timing Variation for 3D IC

    4. No Access

      Book Chapter

      Pages 415-441

      Chip/Package Co-analysis of Mechanical Stress for 3D IC

    5. No Access

      Book Chapter

      Pages 443-465

      3D Chip/Package Co-analysis of Stress-Induced Timing Variations

    6. No Access

      Book Chapter

      Pages 467-489

      TSV Interfacial Crack Analysis and Optimization

  6. Other Topics

    1. Front Matter

      Pages 491-491

    2. No Access

      Book Chapter

      Pages 493-514

      Ultra High Density Logic Designs Using Monolithic 3D Integration

    3. No Access

      Book Chapter

      Pages 515-535

      Impact of TSV Scaling on 3D IC Design Quality

    4. No Access

      Book Chapter

      Pages 537-560

      3D-MAPS: 3D Massively Parallel Processor with Stacked Memory