2011

Low Power Networks-on-Chip

Editors:

ISBN: 978-1-4419-6910-1 (Print) 978-1-4419-6911-8 (Online)

Table of contents (10 chapters)

  1. Front Matter

    Pages i-xix

  2. Low-Level Design Techniques

    1. Front Matter

      Pages 1-1

    2. No Access

      Book Chapter

      Pages 3-20

      Hybrid Circuit/Packet Switched Network for Energy Efficient on-Chip Interconnections

    3. No Access

      Book Chapter

      Pages 21-43

      Run-Time Power-Gating Techniques for Low-Power On-Chip Networks

    4. No Access

      Book Chapter

      Pages 45-69

      Adaptive Voltage Control for Energy-Efficient NoC Links

    5. No Access

      Book Chapter

      Pages 71-109

      Asynchronous Communications for NoCs

  3. System-Level Design Techniques

    1. Front Matter

      Pages 111-111

    2. No Access

      Book Chapter

      Pages 113-150

      Application-Specific Routing Algorithms for Low Power Network on Chip Design

    3. No Access

      Book Chapter

      Pages 151-174

      Adaptive Data Compression for Low-Power On-Chip Networks

    4. No Access

      Book Chapter

      Pages 175-195

      Latency-Constrained, Power-Optimized NoC Design for a 4G SoC: A Case Study

  4. Future and Emerging Technologies

    1. Front Matter

      Pages 197-197

    2. No Access

      Book Chapter

      Pages 199-222

      Design and Analysis of NoCs for Low-Power 2D and 3D SoCs

    3. No Access

      Book Chapter

      Pages 223-254

      CMOS Nanophotonics: Technology, System Implications, and a CMP Case Study

    4. No Access

      Book Chapter

      Pages 255-280

      RF-Interconnect for Future Network-On-Chip

  5. Back Matter

    Pages 281-287