On-Chip Interconnect with aelite

1. Front Matter

   Pages i-ix

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2. Introduction

   • Andreas Hansson, Kees Goossens

   Pages 1-18

3. Proposed Solution

   • Andreas Hansson, Kees Goossens

   Pages 19-39

4. Dimensioning

   • Andreas Hansson, Kees Goossens

   Pages 41-68

5. Allocation

   • Andreas Hansson, Kees Goossens

   Pages 69-102

6. Instantiation

   • Andreas Hansson, Kees Goossens

   Pages 103-120

7. Verification

   • Andreas Hansson, Kees Goossens

   Pages 121-141

8. FPGA Case Study

   • Andreas Hansson, Kees Goossens

   Pages 143-155

9. ASIC Case Study

   • Andreas Hansson, Kees Goossens

   Pages 157-169

10. Related Work

    • Andreas Hansson, Kees Goossens

    Pages 171-180

11. Conclusions and Future Work

    • Andreas Hansson, Kees Goossens

    Pages 181-184

12. Back Matter

    Pages 185-208

    PDF

The book provides a comprehensive description and implementation methodology for the Philips/NXP Aethereal/aelite Network-on-Chip (NoC). The presentation offers a systems perspective, starting from the system requirements and deriving and describing the resulting hardware architectures, embedded software, and accompanying design flow. Readers get an in depth view of the interconnect requirements, not centered only on performance and scalability, but also the multi-faceted, application-driven requirements, in particular composability and predictability. The book shows how these qualitative requirements are implemented in a state-of-the-art on-chip interconnect, and presents the realistic, quantitative costs.

• Embedded Systems
• Interconnect
• Network on Chip
• On-Chip Communication
• On-Chip Interconnect
• System on Chip

• Research & Development, ARM Ltd., Cambridge, United Kingdom

  Andreas Hansson

• Potentiaal/PT 9.34, Faculty of Electrical Engineering, Eindhoven University of Technology, Eindhoven, Netherlands

  Kees Goossens

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