Wafer Level 3-D ICs Process Technology

Editors:

ISBN: 978-0-387-76532-7 (Print) 978-0-387-76534-1 (Online)

Table of contents (17 chapters)

  1. Front Matter

    Pages 1-14

  2. No Access

    Book Chapter

    Pages 1-11

    Overview of Wafer-Level 3D ICs

  3. No Access

    Book Chapter

    Pages 1-17

    Monolithic 3D Integrated Circuits

  4. No Access

    Book Chapter

    Pages 1-17

    Stacked CMOS Technologies

  5. No Access

    Book Chapter

    Pages 1-35

    Wafer-Bonding Technologies and Strategies for 3D ICs

  6. No Access

    Book Chapter

    Pages 1-32

    Through-Silicon Via Fabrication, Backgrind, and Handle Wafer Technologies

  7. No Access

    Book Chapter

    Pages 1-14

    Cu Wafer Bonding for 3D IC Applications

  8. No Access

    Book Chapter

    Pages 1-39

    Cu/Sn Solid–Liquid Interdiffusion Bonding

  9. No Access

    Book Chapter

    Pages 1-26

    An SOI-Based 3D Circuit Integration Technology

  10. No Access

    Book Chapter

    Pages 1-21

    3D Fabrication Options for High-Performance CMOS Technology

  11. No Access

    Book Chapter

    Pages 1-38

    3D Integration Based upon Dielectric Adhesive Bonding

  12. No Access

    Book Chapter

    Pages 1-11

    Direct Hybrid Bonding

  13. No Access

    Book Chapter

    Pages 1-23

    3D Memory

  14. No Access

    Book Chapter

    Pages 1-13

    Circuit Architectures for 3D Integration

  15. No Access

    Book Chapter

    Pages 1-26

    Thermal Challenges of 3D ICs

  16. No Access

    Book Chapter

    Pages 1-20

    Status and Outlook

  17. Back Matter

    Pages 1-7