Design and Analysis of Distributed Embedded Systems

IFIP 17th World Computer Congress — TC10 Stream on Distributed and Parallel Embedded Systems (DIPES 2002) August 25–29, 2002, Montréal, Québec, Canada

ISBN: 978-1-4757-4937-3 (Print) 978-0-387-35599-3 (Online)

Table of contents (28 chapters)

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  1. Front Matter

    Pages i-xi

  2. Modelling and Specification

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      Pages 1-10

      Can UML be a System-Level Language for Embedded Software?

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      Pages 11-20

      PEARL for Distributed Embedded Systems

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      Pages 21-30

      Universal Plug and Play Machine Models

  3. Specification and Analysis

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      Pages 31-40

      Analysis of Event-Driven Real-Time Systems with Time Petri Nets

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      Pages 41-50

      Petri Net Based Design of Reconfigurable Embedded Real-Time Systems

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      Pages 51-60

      Model checking robustness to desynchronization

  4. Verification and Validation

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      Pages 61-69

      A Semi-Formal Method to Verify Correctness of Functional Requirements Specifications of Complex Systems

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      Pages 71-80

      Towards Design Verification and Validation at Multiple Levels of Abstraction

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      Pages 81-90

      Modeling and Verification of Pipelined Embedded Processors in the Presence of Hazards and Exceptions

  5. Fault Tolerance and Detection

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      Pages 91-100

      Statistical Analysis of a Hybrid Replication Model

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      Pages 101-112

      Building Embedded Fault-Tolerant Systems for Critical Applications: An Experimental Study

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      Pages 113-119

      Fault detection in safety-critical embedded systems

  6. Middleware and Reuse

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      Pages 121-130

      Dependability Characterization of Middleware Services

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      Pages 131-140

      Adaptive Middleware for Ubiquitous Computing Environments

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      Pages 141-151

      Finegrained Application Specific Customization of Embedded Software

  7. Timing and Performance Analysis

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      Pages 153-162

      Checking the Temporal Behaviour of Distributed and Parallel Embedded Systems

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      Pages 163-172

      Transforming Execution-Time Boundable Code into Temporally Predictable Code

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      Pages 173-183

      Bottom-Up Performance Analysis of HW/SW Platforms

  8. Partitioning and Scheduling

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      Pages 185-194

      Temporal Partitioning and Sequencing of Dataflow Graphs on Reconfigurable Systems

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      Pages 195-204

      Integration of Low Power Analysis into High-Level Synthesis

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