Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing

10th International Conference, FPL 2000 Villach, Austria, August 27–30, 2000 Proceedings

Editors:

ISBN: 978-3-540-67899-1 (Print) 978-3-540-44614-9 (Online)

Table of contents (101 chapters)

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  1. Invited Keynote

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      Book Chapter

      Pages 1-6

      The Rising Wave of Field Programmability

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      Pages 7-18

      Tightly Integrated Design Space Exploration with Spatial and Temporal Partitioning in SPARCS

  2. Network Processors

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      Pages 19-28

      A Dynamically Reconfigurable FPGA-Based Content Addressable Memory for Internet Protocol Characterization

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      Pages 29-38

      A Compiler Directed Approach to Hiding Configuration Latency in Chameleon Processors

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      Pages 39-47

      Reconfigurable Network Processors Based on Field Programmable System Level Integrated Circuits

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      Pages 48-57

      Internet Connected FPL

  3. Prototyping

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      Pages 58-67

      Field Programmable Communication Emulation and Optimization for Embedded System Design

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      Pages 68-77

      FPGA-Based Emulation: Industrial and Custom Prototyping Solutions

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      Pages 78-86

      FPGA-Based Prototyping for Product Definition

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      Pages 87-95

      Implementation of Virtual Circuits by Means of the FIPSOC Devices

  4. Dynamically Reconfigurable I

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      Pages 96-105

      Static and Dynamic Reconfigurable Designs for a 2D Shape-Adaptive DCT

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      Pages 106-120

      A Self-Reconfigurable Gate Array Architecture

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      Pages 121-130

      Multitasking on FPGA Coprocessors

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      Pages 131-140

      Design Visualisation for Dynamically Reconfigurable Systems

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      Pages 141-150

      Verification of Dynamically Reconfigurable Logic

  5. Miscellaneous I

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      Pages 151-156

      Design of a Fault Tolerant FPGA

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      Pages 157-162

      Real-Time Face Detection on a Configurable Hardware System

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      Pages 163-168

      Multifunctional Programmable Single-Board CAN Monitoring Module

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      Pages 169-174

      Self-Testing of Linear Segments in User-Programmed FPGAs

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      Pages 175-180

      Implementing a Fieldbus Interface Using an FPGA

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