Cryptographic Hardware and Embedded Systems - CHES 2006

8th International Workshop, Yokohama, Japan, October 10-13, 2006. Proceedings

Editors:

ISBN: 978-3-540-46559-1 (Print) 978-3-540-46561-4 (Online)

Table of contents (35 chapters)

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  1. Front Matter

    Pages -

  2. Side Channels I

    1. Book Chapter

      Pages 1-14

      Template Attacks in Principal Subspaces

    2. Book Chapter

      Pages 15-29

      Templates vs. Stochastic Methods

    3. Book Chapter

      Pages 30-45

      Towards Security Limits in Side-Channel Attacks

  3. Low Resources

    1. Book Chapter

      Pages 46-59

      HIGHT: A New Block Cipher Suitable for Low-Resource Device

  4. Invited Talk I

    1. Book Chapter

      Pages 60-60

      Integer Factoring Utilizing PC Cluster

  5. Hardware Attacks and Countermeasures I

    1. Book Chapter

      Pages 61-75

      Optically Enhanced Position-Locked Power Analysis

    2. Book Chapter

      Pages 76-90

      Pinpointing the Side-Channel Leakage of Masked AES Hardware Implementations

    3. Book Chapter

      Pages 91-100

      A Generalized Method of Differential Fault Attack Against AES Cryptosystem

  6. Special Purpose Hardware

    1. Book Chapter

      Pages 101-118

      Breaking Ciphers with COPACOBANA –A Cost-Optimized Parallel Code Breaker

    2. Book Chapter

      Pages 119-133

      Implementing the Elliptic Curve Method of Factoring in Reconfigurable Hardware

  7. Efficient Algorithms for Embedded Processors

    1. Book Chapter

      Pages 134-147

      Implementing Cryptographic Pairings on Smartcards

    2. Book Chapter

      Pages 148-159

      SPA-Resistant Scalar Multiplication on Hyperelliptic Curve Cryptosystems Combining Divisor Decomposition Technique and Joint Regular Form

    3. Book Chapter

      Pages 160-173

      Fast Generation of Prime Numbers on Portable Devices: An Update

  8. Side Channels II

    1. Book Chapter

      Pages 174-186

      A Proposition for Correlation Power Analysis Enhancement

    2. Book Chapter

      Pages 187-200

      High-Resolution Side-Channel Attack Using Phase-Based Waveform Matching

    3. Book Chapter

      Pages 201-215

      Cache-Collision Timing Attacks Against AES

    4. Book Chapter

      Pages 216-230

      Provably Secure S-Box Implementation Based on Fourier Transform

  9. Invited Talk II

    1. Book Chapter

      Pages 231-231

      The Outer Limits of RFID Security

  10. Hardware Attacks and Countermeasures II

    1. Book Chapter

      Pages 232-241

      Three-Phase Dual-Rail Pre-charge Logic

    2. Book Chapter

      Pages 242-254

      Dual-Rail Random Switching Logic: A Countermeasure to Reduce Side Channel Leakage

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