Book Volume 3740 2005

Advances in Computer Systems Architecture

10th Asia-Pacific Conference, ACSAC 2005, Singapore, October 24-26, 2005. Proceedings


ISBN: 978-3-540-29643-0 (Print) 978-3-540-32108-8 (Online)

Table of contents (67 chapters)

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  1. Front Matter

    Pages -

  2. Keynote Address I

    1. Chapter

      Pages 1-2

      Processor Architecture for Trustworthy Computers

  3. Session 1A: Energy Efficient and Power Aware Techniques

    1. Chapter

      Pages 3-14

      Efficient Voltage Scheduling and Energy-Aware Co-synthesis for Real-Time Embedded Systems

    2. Chapter

      Pages 15-27

      Energy-Effective Instruction Fetch Unit for Wide Issue Processors

    3. Chapter

      Pages 28-40

      Rule-Based Power-Balanced VLIW Instruction Scheduling with Uncertainty

    4. Chapter

      Pages 41-51

      An Innovative Instruction Cache for Embedded Processors

    5. Chapter

      Pages 52-64

      Dynamic Voltage Scaling for Power Aware Fast Fourier Transform (FFT) Processor

  4. Session 1B: Methodologies and Architectures for Application-Specific Systems

    1. Chapter

      Pages 65-78

      Design of an Efficient Multiplier-Less Architecture for Multi-dimensional Convolution

    2. Chapter

      Pages 79-89

      A Pipelined Hardware Architecture for Motion Estimation of H.264/AVC

    3. Chapter

      Pages 90-103

      Embedded Intelligent Imaging On-Board Small Satellites

    4. Chapter

      Pages 104-117

      Architectural Enhancements for Color Image and Video Processing on Embedded Systems

    5. Chapter

      Pages 118-130

      A Portable Doppler Device Based on a DSP with High- Performance Spectral Estimation and Output

  5. Session 2A: Processor Architectures and Microarchitectures

    1. Chapter

      Pages 131-142

      A Power-Efficient Processor Core for Reactive Embedded Applications

    2. Chapter

      Pages 143-156

      A Stream Architecture Supporting Multiple Stream Execution Models

    3. Chapter

      Pages 157-170

      The Challenges of Massive On-Chip Concurrency

    4. Chapter

      Pages 171-185

      FMRPU: Design of Fine-Grain Multi-context Reconfigurable Processing Unit

  6. Session 2B: High-Reliability and Fault-Tolerant Architectures

    1. Chapter

      Pages 186-199

      Modularized Redundant Parallel Virtual File System

    2. Chapter

      Pages 200-214

      Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures

    3. Chapter

      Pages 215-228

      A Fault-Tolerant Routing Strategy for Fibonacci-Class Cubes

    4. Chapter

      Pages 229-235

      Embedding of Cycles in the Faulty Hypercube

  7. Session 3A: Compiler and OS for Emerging Architectures

    1. Chapter

      Pages 236-251

      Improving the Performance of GCC by Exploiting IA-64 Architectural Features

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