Advances in Computer Systems Architecture

10th Asia-Pacific Conference, ACSAC 2005, Singapore, October 24-26, 2005. Proceedings

  • Thambipillai Srikanthan
  • Jingling Xue
  • Chip-Hong Chang
Conference proceedings ACSAC 2005

DOI: 10.1007/11572961

Part of the Lecture Notes in Computer Science book series (LNCS, volume 3740)

Table of contents (67 papers)

  1. Front Matter
  2. Keynote Address I

  3. Session 1A: Energy Efficient and Power Aware Techniques

    1. Energy-Effective Instruction Fetch Unit for Wide Issue Processors
      Juan L. Aragón, Alexander V. Veidenbaum
      Pages 15-27
    2. Rule-Based Power-Balanced VLIW Instruction Scheduling with Uncertainty
      Shu Xiao, Edmund M. -K. Lai, A. B. Premkumar
      Pages 28-40
    3. An Innovative Instruction Cache for Embedded Processors
      Cheol Hong Kim, Sung Woo Chung, Chu Shik Jhon
      Pages 41-51
    4. Dynamic Voltage Scaling for Power Aware Fast Fourier Transform (FFT) Processor
      David Fitrio, Jugdutt Singh, Aleksandar Stojcevski
      Pages 52-64
  4. Session 1B: Methodologies and Architectures for Application-Specific Systems

    1. Design of an Efficient Multiplier-Less Architecture for Multi-dimensional Convolution
      Ming Z. Zhang, Hau T. Ngo, Vijayan K. Asari
      Pages 65-78
    2. A Pipelined Hardware Architecture for Motion Estimation of H.264/AVC
      Su-Jin Lee, Cheong-Ghil Kim, Shin-Dug Kim
      Pages 79-89
    3. Embedded Intelligent Imaging On-Board Small Satellites
      Siti Yuhaniz, Tanya Vladimirova, Martin Sweeting
      Pages 90-103
    4. Architectural Enhancements for Color Image and Video Processing on Embedded Systems
      Jongmyon Kim, D. Scott Wills, Linda M. Wills
      Pages 104-117
    5. A Portable Doppler Device Based on a DSP with High- Performance Spectral Estimation and Output
      Yufeng Zhang, Yi Zhou, Jianhua Chen, Xinling Shi, Zhenyu Guo
      Pages 118-130
  5. Session 2A: Processor Architectures and Microarchitectures

    1. A Power-Efficient Processor Core for Reactive Embedded Applications
      Lei Yang, Morteza Biglari-Abhari, Zoran Salcic
      Pages 131-142
    2. A Stream Architecture Supporting Multiple Stream Execution Models
      Nan Wu, Mei Wen, Haiyan Li, Li Li, Chunyuan Zhang
      Pages 143-156
    3. The Challenges of Massive On-Chip Concurrency
      Kostas Bousias, Chris Jesshope
      Pages 157-170
  6. Session 2B: High-Reliability and Fault-Tolerant Architectures

    1. Modularized Redundant Parallel Virtual File System
      Sheng-Kai Hung, Yarsun Hsu
      Pages 186-199
    2. Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures
      Jie S. Hu, G. M. Link, Johnsy K. John, Shuai Wang, Sotirios G. Ziavras
      Pages 200-214
    3. A Fault-Tolerant Routing Strategy for Fibonacci-Class Cubes
      Zhang Xinhua, Peter K. K. Loh
      Pages 215-228
    4. Embedding of Cycles in the Faulty Hypercube
      Sun-Yuan Hsieh
      Pages 229-235

About these proceedings


On behalf of the ProgramCommittee, we are pleased to present the proceedings of the 2005 Asia-Paci?c Computer Systems Architecture Conference (ACSAC 2005) held in the beautiful and dynamic country of Singapore. This conference was the tenth in its series, one of the leading forums for sharing the emerging research ?ndings in this ?eld. In consultation with the ACSAC Steering Committee, we selected a - member Program Committee. This Program Committee represented a broad spectrum of research expertise to ensure a good balance of research areas, - stitutions and experience while maintaining the high quality of this conference series. This year’s committee was of the same size as last year but had 19 new faces. We received a total of 173 submissions which is 14% more than last year. Each paper was assigned to at least three and in some cases four ProgramC- mittee members for review. Wherever necessary, the committee members called upon the expertise of their colleagues to ensure the highest possible quality in the reviewing process. As a result, we received 415 reviews from the Program Committee members and their 105 co-reviewers whose names are acknowledged inthe proceedings.Theconferencecommitteeadopteda systematicblind review process to provide a fair assessment of all submissions. In the end, we accepted 65 papers on a broad range of topics giving an acceptance rate of 37.5%. We are grateful to all the Program Committee members and the co-reviewers for their e?orts in completing the reviews within a tight schedule.


Routing Scheduling Session TCP/IP algorithms caching computer architecture embedded systems high-performance architecture image processing interconnection networks microarchitectures network computing processor reconfigurable architecture

Editors and affiliations

  • Thambipillai Srikanthan
    • 1
  • Jingling Xue
    • 2
  • Chip-Hong Chang
    • 3
  1. 1.Centre for High Performance Embedded Systems, School of Computer EngineeringNanyang Technological UniversitySingapore
  2. 2.National ICTAustralia
  3. 3.Centre for High Performance Embedded SystemsNanyang Technological UniversitySingapore

Bibliographic information

  • Copyright Information Springer-Verlag Berlin Heidelberg 2005
  • Publisher Name Springer, Berlin, Heidelberg
  • eBook Packages Computer Science
  • Print ISBN 978-3-540-29643-0
  • Online ISBN 978-3-540-32108-8
  • Series Print ISSN 0302-9743
  • Series Online ISSN 1611-3349