2005

New Algorithms, Architectures and Applications for Reconfigurable Computing

Editors:

ISBN: 978-1-4020-3127-4 (Print) 978-1-4020-3128-1 (Online)

Table of contents (24 chapters)

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  1. Architectures

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      Book Chapter

      Pages 3-13

      Extra-dimensional Island-Style FPGAs

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      Book Chapter

      Pages 15-28

      A Tightly Coupled VLIW/Reconfigurable Matrix and its Modulo Scheduling Technique

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      Pages 29-42

      Stream-based XPP Architectures in Adaptive System-on-Chip Integration

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      Pages 43-54

      Core-Based Architecture for Data Transfer Control in SoC Design

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      Book Chapter

      Pages 55-66

      Customizable and Reduced Hardware Motion Estimation Processors

  2. Methodologies and Tools

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      Book Chapter

      Pages 69-80

      Enabling Run-time Task Relocation on Reconfigurable Systems

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      Pages 81-91

      A Unified Codesign Environment

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      Pages 93-103

      Mapping Applications to a Coarse Grain Reconfigurable System

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      Pages 105-115

      Compilation and Temporal Partitioning for a Coarse-grain Reconfigurable Architecture

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      Pages 117-129

      Run-time Defragmentation for Dynamically Reconfigurable Hardware

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      Pages 131-143

      Virtual Hardware Byte Code as a Design Platform for Reconfigurable Embedded Systems

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      Pages 145-155

      A Low Energy Data Management for Multi-Context Reconfigurable Architectures

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      Book Chapter

      Pages 157-168

      Dynamic and Partial Reconfiguration in FPGA SoCs: Requirements Tools and a Case Study

  3. Applications

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      Book Chapter

      Pages 171-181

      Design Flow for a Reconfigurable Processor

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      Book Chapter

      Pages 183-194

      IPsec-Protected Transport of HDTV over IP

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      Book Chapter

      Pages 195-207

      Fast, Large-scale String Match for a 10 Gbps FPGA-based NIDS

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      Book Chapter

      Pages 209-218

      Architecture and FPGA Implementation of a Digit-serial RSA Processor

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      Book Chapter

      Pages 219-229

      Division in GF(p) for Application in Elliptic Curve Cryptosystems on Field Programmable Logic

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      Book Chapter

      Pages 231-249

      A New Arithmetic Unit in GF(2M) for Reconfigurable Hardware Implementation

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      Book Chapter

      Pages 251-264

      Performance Analysis of SHACAL-1 Encryption Hardware Architectures

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