Book 2005

New Algorithms, Architectures and Applications for Reconfigurable Computing


ISBN: 978-1-4020-3127-4 (Print) 978-1-4020-3128-1 (Online)

Table of contents (24 chapters)

previous Page of 2
  1. Front Matter

    Pages i-xvii

  2. Architectures

    1. Chapter

      Pages 3-13

      Extra-dimensional Island-Style FPGAs

    2. Chapter

      Pages 15-28

      A Tightly Coupled VLIW/Reconfigurable Matrix and its Modulo Scheduling Technique

    3. Chapter

      Pages 29-42

      Stream-based XPP Architectures in Adaptive System-on-Chip Integration

    4. Chapter

      Pages 43-54

      Core-Based Architecture for Data Transfer Control in SoC Design

    5. Chapter

      Pages 55-66

      Customizable and Reduced Hardware Motion Estimation Processors

  3. Methodologies and Tools

    1. Chapter

      Pages 69-80

      Enabling Run-time Task Relocation on Reconfigurable Systems

    2. Chapter

      Pages 81-91

      A Unified Codesign Environment

    3. Chapter

      Pages 93-103

      Mapping Applications to a Coarse Grain Reconfigurable System

    4. Chapter

      Pages 105-115

      Compilation and Temporal Partitioning for a Coarse-grain Reconfigurable Architecture

    5. Chapter

      Pages 117-129

      Run-time Defragmentation for Dynamically Reconfigurable Hardware

    6. Chapter

      Pages 131-143

      Virtual Hardware Byte Code as a Design Platform for Reconfigurable Embedded Systems

    7. Chapter

      Pages 145-155

      A Low Energy Data Management for Multi-Context Reconfigurable Architectures

    8. Chapter

      Pages 157-168

      Dynamic and Partial Reconfiguration in FPGA SoCs: Requirements Tools and a Case Study

  4. Applications

    1. Chapter

      Pages 171-181

      Design Flow for a Reconfigurable Processor

    2. Chapter

      Pages 183-194

      IPsec-Protected Transport of HDTV over IP

    3. Chapter

      Pages 195-207

      Fast, Large-scale String Match for a 10 Gbps FPGA-based NIDS

    4. Chapter

      Pages 209-218

      Architecture and FPGA Implementation of a Digit-serial RSA Processor

    5. Chapter

      Pages 219-229

      Division in GF(p) for Application in Elliptic Curve Cryptosystems on Field Programmable Logic

    6. Chapter

      Pages 231-249

      A New Arithmetic Unit in GF(2M) for Reconfigurable Hardware Implementation

    7. Chapter

      Pages 251-264

      Performance Analysis of SHACAL-1 Encryption Hardware Architectures

previous Page of 2