Design, Analysis and Test of Logic Circuits Under Uncertainty

1. Front Matter

   Pages i-xi

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2. Introduction

   • Smita Krishnaswamy, Igor L. Markov, John P. Hayes

   Pages 1-19

3. Probabilistic Transfer Matrices

   • Smita Krishnaswamy, Igor L. Markov, John P. Hayes

   Pages 21-36

4. Computing with Probabilistic Transfer Matrices

   • Smita Krishnaswamy, Igor L. Markov, John P. Hayes

   Pages 37-52

5. Testing Logic Circuits for Probabilistic Faults

   • Smita Krishnaswamy, Igor L. Markov, John P. Hayes

   Pages 53-61

6. Signature-Based Reliability Analysis

   • Smita Krishnaswamy, Igor L. Markov, John P. Hayes

   Pages 63-91

7. Design for Robustness

   • Smita Krishnaswamy, Igor L. Markov, John P. Hayes

   Pages 93-113

8. Summary and Extensions

   • Smita Krishnaswamy, Igor L. Markov, John P. Hayes

   Pages 115-120

9. Back Matter

   Pages 121-123

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Logic circuits are becoming increasingly susceptible to probabilistic behavior caused by external radiation and process variation. In addition, inherently probabilistic quantum- and nano-technologies are on the horizon as we approach the limits of CMOS scaling. Ensuring the reliability of such circuits despite the probabilistic behavior is a key challenge in IC design---one that necessitates a fundamental, probabilistic reformulation of synthesis and testing techniques. This monograph will present techniques for analyzing, designing, and testing logic circuits with probabilistic behavior.

• Fault-tolerance
• Probabilistic logic
• Reliability
• Soft errors
• Uncertainty

• , Dept. of Biological Sciences, Columbia University, New York, USA

  Smita Krishnaswamy

• , Dept. of EECS, University of Michigan, Ann Arbor, USA

  Igor L. Markov, John P. Hayes

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