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Delta-Sigma A/D-Converters

Practical Design for Communication Systems

  • Book
  • © 2013

Overview

Authors:
  1. Richard Gaggl

    1. Infineon Technologies Austria AG, Villach, Austria

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  • Gives a comprehensive introduction into practical design and implementation of delta-sigma modulators employing discrete-time and continuous-time loop-filters
  • Gives a detailed description and lab analysis of 3 different A/D converter solutions used in high volume low-power and low-voltage CMOS products
  • Focuses on robustness for low-power and small chip area design which is mandatory for industrial solutions
  • Includes supplementary material: sn.pub/extras

Part of the book series: Springer Series in Advanced Microelectronics (MICROELECTR.)

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Table of contents (6 chapters)

  1. Front Matter

    Pages I-XVIII
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  2. Introduction

    • Richard Gaggl
    Pages 1-13

  3. Limitations of Delta-Sigma Converters

    • Richard Gaggl
    Pages 15-53

  4. A Delta-Sigma Converter with Dynamic-Biasing Technique

    • Richard Gaggl
    Pages 55-73

  5. A Feed-Forward Delta-Sigma Converter for ADSL

    • Richard Gaggl
    Pages 75-88

  6. A Delta-Sigma Converter for WLAN Using a TEQ

    • Richard Gaggl
    Pages 89-125

  7. Conclusions

    • Richard Gaggl
    Pages 127-137

  8. Back Matter

    Pages 139-145
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Keywords

About this book

The emphasis of this book is on practical design aspects for broadband A/D converters for communication systems. The embedded designs are employed for transceivers in the field of ADSL solutions and WLAN applications. An area- and power-efficient realization of a converter is mandatory to remain competitive in the market. The right choice for the converter topology and architecture needs to be done very carefully to result in a competitive FOM. The book begins with a brief overview of basic concepts about ADSL and WLAN to understand the ADC requirements. At architectural level, issues on different modulator topologies are discussed employing the provided technology node. The design issues are pointed out in detail for modern digital CMOS technologies, beginning with 180nm followed by 130nm and going down to 65nm feature size. Beside practical aspects, challenges to mixed-signal design level are addressed to optimize the converters in terms of consumed chip area, power consumption and design for high yield in volume production. Thus, careful considerations on circuit- and architectural- level are performed by introducing a dynamic-biasing technique, a feed-forward approach and a resolution in time instead of amplitude resolution.

Authors and Affiliations

  • Infineon Technologies Austria AG, Villach, Austria

    Richard Gaggl

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