Abstract
A 37 GHz wide-band programmable divide-by-N frequency divider (FD) composed of a divide-by-2 divider (acting as the first stage) and a divider with a division ratio range of 273–330 (acting as the second stage) has been designed and fabricated using standard 90 nm CMOS technology. The second stage divider consists of a high-speed divide-by-8/9 dual-modulus prescaler, a pulse counter, and a swallow counter. Both the first stage divider (with high speed) and the divide-by-8/9 prescaler employ dynamic current-mode logic (DCML) structure to improve the operating performance. The first stage divider can work from 2 to 40 GHz and the whole divider covers a wide frequency range from 25 to 37 GHz. The input sensitivity is as low as −20 dBm at 32 GHz and the phase noise at 37 GHz is less than −130 dBc/Hz at an offset of 1 MHz. The whole chip dissipates 17.88 mW at a supply voltage of 1.2 V and occupies an area of only 730 μm ×475 μm.
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Project supported by the National Basic Research Program of China (No. 2010CB327404) and the National Natural Science Foundation of China (No. 60901012)
ORCID: Ting GUO, http://orcid.org/0000-0002-7853-7479
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Guo, T., Li, Zq., Li, Q. et al. A 37 GHz wide-band programmable divide-by-N frequency divider for millimeter-wave silicon-based phase-locked loop frequency synthesizers. J. Zhejiang Univ. - Sci. C 15, 1200–1210 (2014). https://doi.org/10.1631/jzus.C1400091
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DOI: https://doi.org/10.1631/jzus.C1400091
Key words
- Wide-band
- Divide-by-N
- Frequency divider
- Dynamic current-mode logic (DCML)
- Pulse and swallow counters
- CMOS