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Method of simulation the asymmetric memory access for solving synchronization problems in multiprocessor systems

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Abstract

A method and algorithm for accelerating the simulation in the route of the joint hardware-software verification of Multicore systems-on-chip (SoC) are developed. An approach with the peculiarity of simulating the asymmetric memory access, which provides the solution for the synchronization problem in multiprocessor systems with a considerable increase in performance as compared to the simulation of the RTL model, is proposed.

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Authors and Affiliations

  1. National Research University of Electronic Technology (MIET), Moscow, Russia

    V. S. Gavrilov & G. G. Kazennov

Authors
  1. V. S. Gavrilov
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  2. G. G. Kazennov
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Correspondence to V. S. Gavrilov.

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Original Russian Text © V.S. Gavrilov, G.G. Kazennov, 2013, published in Izvestiya Vysshikh Uchebnykh Zavedenii. Elektronika, 2013, No. 2(100), pp. 59–65.

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Gavrilov, V.S., Kazennov, G.G. Method of simulation the asymmetric memory access for solving synchronization problems in multiprocessor systems. Russ Microelectron 43, 496–500 (2014). https://doi.org/10.1134/S1063739714070087

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  • DOI: https://doi.org/10.1134/S1063739714070087

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