Abstract
Development of test programs and analysis of the results of their execution is the basic approach to verification of microprocessors at the system level. There is a variety of methods for the automation of test generation, starting with the generation of random code and ending with directed model-based test generation. However, there is no cure-all method. In practice, combinations of various complementary techniques are used. Unfortunately, no solution for the integration of various test generation methods into a unified environment is currently available. To test a microprocessor, verification engineers are forced to use many different test generators, which results in a number of difficulties, such as (1) the necessity to ensure the compatibility of tool configurations (in each tool, a specific description of the target microprocessor is used, which leads to duplication of information); (2) the necessity to develop utilities for integration tools (different tools have different interfaces and use different data formats). This paper describes a concept of extensible environment for test program generation for microprocessors. This environment provides a unified approach for test generation; it supports widespread test generation techniques, and can be extended by new testing tools. The proposed concept was partially implemented in MicroTESK (Microprocessor T Esting and Specification Kit).
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
M.S. Abadir and S. Dasgupta, Guest editors’ introduction: Microprocessor test and verification, IEEE Design & Test Comput., 2000, vol. 17, no. 4, pp. 4–5.
Kamkin, A.S., Test program generation for microprocessors, in Trudy Instituta Sistemnogo Programmirovaniya Ross. Akad. Nauk, 2008, vol. 14, part 2, pp. 23–63.
http://www.arm.com/community/partners/displayproduct/rw/ProductId/5171/
Adir, A., Almog, E., Fournier, L., Marcus, E., Rimon, M., Vinov, M., and Ziv. A., Genesys-Pro: Innovations in test program generation for functional processor verification, IEEE Design & Test Comput., 2004, vol. 21, no. 2, pp. 84–93.
Mishra, P. and Dutt, N., Specification-driven directed test generation for validation of pipelined processors, ACM Trans. Design Autom. Electron. Syst. (TODAES), 2008, vol. 13, no. 3, pp. 1–36.
Kamkin, A.S., Some issues of automation of test program generation for branch units of microprocessors, in Trudy Instituta Sistemnogo Programmirovaniya Ross. Akad. Nauk, 2010, vol. 18, pp. 129–150.
Naveh, Y., Rimon, M., Jaeger, I., Katz, Y., Vinov, M., Marcus, E., and Shurek, G., Constraint-based random stimuli generation for hardware verification, AI Magazine, 2007, vol. 28, no. 3, pp. 13–30.
Grun, P., Halambi, A., Khare, A., Ganesh, V., Dutt, N., and Nicolau, A., EXPRESSION: An ADL for system level design exploration, Technical Report 1998-29, Univ. of California, Irvine, 1998.
Dang, T.N., Roychoudhury, A., Mitra, T., and Mishra, P., Generating test programs to cover pipeline interactions, in Design Automation Conference (DAC), 2009, pp. 142–147.
Kamkin, A., Kornykhin, E., and Vorobyev, D., Reconfigurable model-based test program generator for microprocessors, in Software Testing, Verification, and Validation Workshops (ICSTW), 2011, pp. 47–54.
Dutertre, B. and Moura, L., The YICES SMT solver, 2006. http://yices.csl.sri.com/tool-paper.pdf
Moura, L. and Bjoslashrner, N., Z3: An efficient SMT solver, in Conf. on Tools and Algorithms for the Construction and Analysis of Systems (TACAS), 2008, pp. 337–340.
Cok, D.R., The SMT-LIBv2 Language and Tools: A Tutorial, GrammaTech, Inc., 2011, Version 1.1.
Aharoni, M., Asaf, S., Fournier, L., Koifman, A., and Nagel, R., FPgen-A test generation framework for datapath floating-point verification, in High Level Design Validation and Test Workshop (HLDVT), 2003, pp. 17–22.
Freericks, M., The nML machine description formalism, Technical Report, Bericht 1991/15, Technische Universitaumlautt Berlin, 1991.
Moona, R., Processor models for retargetable tools, in Int. Workshop on Rapid Systems Prototyping (RSP), 2000, pp. 34–39.
MIPS64TM Architecture for Programmers, Vol. II: The MIPS64TM Instruction Set, Document Number: MD00087, Revision 2.00, June 9, 2003.
Kamkin, A.S. and Chupilko, M.M., Testing microprocessor floating point arithmetic modules for conformity to the IEEE 754 standard, in Trudy Instituta Sistemnogo Programmirovaniya Ross. Akad. Nauk, 2008, no. 2, pp. 7–22.
Kornykhin, E.V., Generation of test data for verification of caching mechanisms and address translation in microprocessors, Program. Comput. Software, 2010, vol. 36, no. 1, pp 28–35.
Author information
Authors and Affiliations
Corresponding author
Additional information
Original Russian Text © A.S. Kamkin, T.I. Sergeeva, S.A. Smolov, A.D. Tatarnikov, M.M. Chupilko, 2014, published in Programmirovanie, 2014, Vol. 40, No. 1.
Rights and permissions
About this article
Cite this article
Kamkin, A.S., Sergeeva, T.I., Smolov, S.A. et al. Extensible environment for test program generation for microprocessors. Program Comput Soft 40, 1–9 (2014). https://doi.org/10.1134/S0361768814010046
Received:
Published:
Issue Date:
DOI: https://doi.org/10.1134/S0361768814010046