Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System

  • Marlene Wan
  • Hui Zhang
  • Varghese George
  • Martin Benes
  • Arthur Abnous
  • Vandana Prabhu
  • Jan Rabaey
Article

DOI: 10.1023/A:1008159121620

Cite this article as:
Wan, M., Zhang, H., George, V. et al. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology (2001) 28: 47. doi:10.1023/A:1008159121620

Abstract

In this paper, we first present a reconfigurable architecture template for low-power digital signal processing, and then an energy conscious design methodology to bridge the algorithm to architecture gap. The energy efficiency of such an architecture and the effectiveness of the methodology are demonstrated in case study implementations targeting baseband voice processing and digital signal processing.

reconfigurable architecture digital signal processor low-power design methodology 

Copyright information

© Kluwer Academic Publishers 2001

Authors and Affiliations

  • Marlene Wan
    • 1
  • Hui Zhang
    • 1
  • Varghese George
    • 1
  • Martin Benes
    • 1
  • Arthur Abnous
    • 1
  • Vandana Prabhu
    • 1
  • Jan Rabaey
    • 1
  1. 1.Electrical Engineering and Computer SciencesUniversity of California at BerkeleyBerkeleyUSA