Cluster Computing

, Volume 5, Issue 1, pp 33–42

High Performance Network of PC Cluster Maestro

Authors

  • Koichi Wada
    • Institute of Information Sciences and ElectronicsUniversity of Tsukuba
  • Shinichi Yamagiwa
    • Institute of Information Sciences and ElectronicsUniversity of Tsukuba
  • Munehiro Fukuda
    • Institute of Information Sciences and ElectronicsUniversity of Tsukuba
Article

DOI: 10.1023/A:1012788521068

Cite this article as:
Wada, K., Yamagiwa, S. & Fukuda, M. Cluster Computing (2002) 5: 33. doi:10.1023/A:1012788521068

Abstract

This paper presents a design, an architecture, and performance evaluation of high-performance network of PC cluster, called Maestro. Most networks of recent clusters have been organized based on WAN or LAN technology, due to their market availability. However, communication protocols and functions of such conventional networks are not optimal for parallel computing, which requires low latency and high bandwidth communication. In this paper, we propose two optimizations for high-performance communication: (1) transferring in burst as many packets as the receiving buffer accepts at once, and (2) having each hardware component pass one data unit to another in a pipelined manner. We have developed a network interface and a switch, which are composed of dedicated hardware modules to realize these optimizations. An implementatin of the message passing library developed on Maestro cluster is also described. Performance evaluation shows that the proposed optimizations can extract the potential performance of the physical layer efficiently and improve the performance in communication.

PC clusternetwork architectureprotocolmessage passingperformance evaluation

Copyright information

© Kluwer Academic Publishers 2002