High Performance Network of PC Cluster Maestro
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This paper presents a design, an architecture, and performance evaluation of high-performance network of PC cluster, called Maestro. Most networks of recent clusters have been organized based on WAN or LAN technology, due to their market availability. However, communication protocols and functions of such conventional networks are not optimal for parallel computing, which requires low latency and high bandwidth communication. In this paper, we propose two optimizations for high-performance communication: (1) transferring in burst as many packets as the receiving buffer accepts at once, and (2) having each hardware component pass one data unit to another in a pipelined manner. We have developed a network interface and a switch, which are composed of dedicated hardware modules to realize these optimizations. An implementatin of the message passing library developed on Maestro cluster is also described. Performance evaluation shows that the proposed optimizations can extract the potential performance of the physical layer efficiently and improve the performance in communication.
- Altera Corporation, Data Book (1998).
- R. Breyer and S. Riley, Switched and Fast Ethernet, 2nd edn. (Ziff Davis Press, 1996).
- R. Buyya, High Performance Cluster Computing: Architectures and Systems, Vol. 1 (Prentice-Hall, 1999).
- R. Buyya, High Performance Cluster Computing: Architectures and Systems, Vol. 2 (Prentice-Hall, 1999).
- N.J. Boden et al., Myrinet — A gigabit-per-second local-area network, IEEE Micro 15(1) (1995).
- T. von Eicken et al., U-Net: A user level network interface for parallel and distributed computing, in: 15th ACM Symposium on Operating Systems Principles (1995) pp. 40–53.
- IEEE Standard Department, IEEE Standard for a High Performance Serial Bus, http://www.1394ta.org (1994).
- V. Karamcheti and A. Chien, Software overhead in messaging layers: Where does the time go? in: Proceedings of International Conference on Architectural Support of Programming Languages and Operating Systems (ASPLOS-VI) (1994) pp. 526–531.
- M. Lauria, S. Pakin and A. Chien, Efficient layering for high speed communication: Fast messages 2.x, in: Proceedings of the 7th High Performance Distributed Computing (HPDC7) Conference (1998).
- Motorola, MPC603e & EC603e RISC Microprocessors Users Manual, http://www.mot.com (1997).
- S. Pakin, V. Karamcheti and A. Chien, Fast messages (FM): Effi-cient, portable communication for workstation clusters and massivelyparallel processors, IEEE Concurrency 5(2) (1997) 60–73.
- M. Matsuda et al., Network interface active messages on SMP clusters, Technical Report on IPSJ SIGARC 72(19) (1998) 55–60.
- S. Yamagiwa, M. Fukuda and K. Wada, Optimization of communication path for cluster computing — development and performance evaluation of Maestro network, Tech. Rep. in Institute of Information Sciences and Electronics, Univ. of Tsukuba, No. ISE-TR–00–166 (2000).
- PCI Special Interest Group, PCI Local Bus Specification, Rev. 2.1 (1995).
- PLX Technology, PCI9060 Data Sheet Ver. 1.2 (1995).
- L. Prylli and B. Tourancheau, BIP: a new protocol designed for high performance networking on myrinet, in: Workshop PC-NOW, IPPS/SPDP98 (Elsevier, Amsterdam, 1998).
- A. Rubini and A. Oram, Linux Device Drivers (O'Reilly & Associates, 1998) ch. 13.
- H. Tezuka et al., PM: An Operating System Coordinated High Performance Communication Library, Lecture Notes in Computer Science, Vol. 1225 (Springer, Amsterdam, 1997) pp. 708–717.
- S. Sumiyoshi et al., The design and evaluation of high performance communication library using a gigabit Ethernet, Technical Report on IPSJ SIGHPC 72(19) (1998) 109–114.
- High Performance Network of PC Cluster Maestro
Volume 5, Issue 1 , pp 33-42
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- Kluwer Academic Publishers
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- PC cluster
- network architecture
- message passing
- performance evaluation
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