Multilevel Reverse-Carry Addition: Single and Dual Adders
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The multilevel reverse-carry approach has been proposed previously for fast computation of the most-significant carry of an adder. In this paper, this approach is extended to generate several carries and is applied to the implementation of single and dual adders. Specifically, the operands are split into blocks and each block is added to produce the sum and the sum plus one. Concurrently with these additions the multilevel reverse-carry approach is used to generate the input carries of these blocks. Finally, these carries are used to select among the sum and the sum plus one.
The delay and complexity of the resulting architecture for a 64-bit adder has been estimated, considering the load introduced by long connections, resulting in a reduction of about 15% in the critical path delay and comparable complexity with respect to traditional implementations of prefix-tree based adders.
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- Multilevel Reverse-Carry Addition: Single and Dual Adders
Journal of VLSI signal processing systems for signal, image and video technology
Volume 33, Issue 1-2 , pp 55-74
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- computer arithmetic
- prefix adders
- dual adders
- most-significant-carry detection
- VLSI design
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