Multilevel Reverse-Carry Addition: Single and Dual Adders

  • J.D. Bruguera
  • T. Lang

DOI: 10.1023/A:1021141818191

Cite this article as:
Bruguera, J. & Lang, T. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology (2003) 33: 55. doi:10.1023/A:1021141818191


The multilevel reverse-carry approach has been proposed previously for fast computation of the most-significant carry of an adder. In this paper, this approach is extended to generate several carries and is applied to the implementation of single and dual adders. Specifically, the operands are split into blocks and each block is added to produce the sum and the sum plus one. Concurrently with these additions the multilevel reverse-carry approach is used to generate the input carries of these blocks. Finally, these carries are used to select among the sum and the sum plus one.

The delay and complexity of the resulting architecture for a 64-bit adder has been estimated, considering the load introduced by long connections, resulting in a reduction of about 15% in the critical path delay and comparable complexity with respect to traditional implementations of prefix-tree based adders.

computer arithmetic prefix adders dual adders most-significant-carry detection VLSI design 

Copyright information

© Kluwer Academic Publishers 2003

Authors and Affiliations

  • J.D. Bruguera
    • 1
  • T. Lang
    • 2
  1. 1.Department of Electronic and Computer EngineeringUniversity of Santiago de CompostelaSantiago de CompostelaSpain
  2. 2.Department of Electrical and Computer EngineeringUniversity of California at IrvineIrvineUSA

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