Journal of VLSI signal processing systems for signal, image and video technology

, Volume 32, Issue 3, pp 207–222

Evaluation of CORDIC Algorithms for FPGA Design

Authors

  • Javier Valls
    • Department of Ingenieria ElectronicaUniversidad Politecnica de Valencia
  • Martin Kuhlmann
    • Broadcom Corporation
  • Keshab K. Parhi
    • Broadcom Corporation
Article

DOI: 10.1023/A:1020205217934

Cite this article as:
Valls, J., Kuhlmann, M. & Parhi, K.K. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology (2002) 32: 207. doi:10.1023/A:1020205217934

Abstract

This paper presents a study of the suitability for FPGA design of full custom based CORDIC implementations. Since all these methods are based on redundant arithmetic, the FPGA implementation of the required operators to perform the different CORDIC methods has been evaluated. Efficient mappings on FPGA have been performed leading to the fastest implementations. It is concluded that the redundant arithmetic operators require a 4 to 5 times larger area than the conventional architecture and the speed advantages of the full custom design has been lost. That is due to the longer routing delays caused by the increase of the fan-out and the number of nets. Therefore, the redundant arithmetic based CORDIC methods are not suitable for FPGA implementation, and the conventional two's complement architecture leads to the best performance.

CORDICFPGATwo's complementredundant arithmetic

Copyright information

© Kluwer Academic Publishers 2002