Journal of Electronic Testing

, Volume 18, Issue 4, pp 415–434

A Novel Reconfigurable Wrapper for Testing of Embedded Core-Based SOCs and its Associated Scheduling Algorithm

  • Sandeep Koranne
Article

DOI: 10.1023/A:1016593423844

Cite this article as:
Koranne, S. Journal of Electronic Testing (2002) 18: 415. doi:10.1023/A:1016593423844

Abstract

In this paper a mathematical formulation and an efficient solution, of the embedded core-based system-on-chip (SOC) test scheduling problem (ECTSP) is presented. The ECTSP can be stated as follows; given a chip with NC cores each having a test Ti; where Ti takes time \(F\) to execute on a test access mechanism (TAM) of width wj, and a constraint W on the number of top-level test pins; calculate the TAM assignment vector π and the schedule Σ for each test Ti, such that the completion time of the full chip test is minimized. All existing approaches have solved the ECTSP by solving the TAM partition and scheduling problem sequentially. In this paper we present an unified approach to solve the ECTSP. We present the first report of a design of reconfigurable core wrapper which allows for a dynamic change in the width of the test access mechanism (TAM) executing a core test. An automatic procedure for the creation of DfT hardware required for reconfiguration using a graph theoretic representation of core wrappers is also presented. For the case of reconfigurable wrappers, efficient algorithms to compute the schedule are presented based upon some recent results in the field of malleable task scheduling. Cases in which the degree of reconfigurability are constrained are considered; the case when only a single core can have reconfigurable wrapper, a schedule with zero TAM idle time can be found in time O(NC(NC + W)lgW), and the case when only 2 different wrapper configurations are allowed can be solved in time O(NC3). Comparison with existing results on benchmark SOCs show that our algorithms outperform state-of-art ILP formulations not only in schedule makespan, but also significantly reduce computation time.

embedded core based test scheduling system-on-chip test reconfigurable wrapper parallel scheduling of malleable tasks VLSI test 

Copyright information

© Kluwer Academic Publishers 2002

Authors and Affiliations

  • Sandeep Koranne
    • 1
  1. 1.Tanner Research, Inc.PasadenaUSA