An Integrated Approach to Testing Embedded Cores and Interconnects Using Test Access Mechanism (TAM) Switch
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The present paper introduces a new strategy for testing embedded cores using Test Access Mechanism (TAM) switches. An algorithm has been proposed for testing the cores using the TAM switch architecture. In addition, a scheme for testing the interconnections between cores in parallel is also presented. Experiments have been carried out on several synthetic SOC benchmarks. Results show significant optimization of area overhead as well as test time.
- D. Bagchi, D.R. Chowdhury, and J. Mukherjee, “A Novel Strategy to Test Core Based Designs, ” VLSi Design, pp. 122–127, 2001.
- K. Chakrabarty, “Test Scheduling for Core-Based Systems, ” in Proc. Intl. Conf. on Computer Aided Design (ICCAD), Nov. 1999, pp. 391–394.
- K. Chakrabarty, “Design of a System-on a Chip Test Access Architectures Using Integer Linear Programming, ” VTS 2000, pp. 127–134.
- K. Chakrabarty, “Design of System-on-a-Chip Test Access Architectures Using Integer Linear Programming, ” in Proc. IEEE VLSI Test Symposium (VTS), Montreal, Canada, April 2000, pp. 127–134.
- K. Chakrabarty, “Design of System-on-a-Chip Test Access Architectures Under Place-and-Route and Power Constraints, ” in Proc. ACM/IEEE Design Automation Conference (DAC), Los Angeles, CA, June 2000, pp. 432–437.
- Chakrabarty, K. (2000) Test Scheduling for Core-Based Systems Using Mixed Integer Linear Programming. IEEE TCAD 19: pp. 1163-1174
- I. Ghosh, S. Dey, and N.K. Jha, “A Fast and Low Cost Technique for Core-Based System-on-Chip, ” in Proc. Design Automation Conference, San Francisco, CA, June 1998.
- E.J. Marinissen et al., “A Structured and Scalable Mechanism for Test Access to Embedded Reusable Cores, ” in Proc. Intl. Test Conference, Washington DC, Oct. 1998.
- E.J. Marinissen, S.K. Goel, and M. Lousberg, “Wrapper Design for Embedded Core Test, ” in Proc. IEEE Intl. Test Conference, Oct. 2000.
- Y. Zorian, E.J. Marinissen, and S. Dey, “Testing Embedded-Core Based System Chips, ” in Proc. Intl. Test Conference,Washington DC, Oct. 1998.
- An Integrated Approach to Testing Embedded Cores and Interconnects Using Test Access Mechanism (TAM) Switch
Journal of Electronic Testing
Volume 18, Issue 4-5 , pp 475-485
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- Kluwer Academic Publishers
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- TAM switch
- interconnect testing
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