The Journal of Supercomputing

, Volume 19, Issue 1, pp 57–75

Optimization of Dynamic Hardware Reconfigurations

Authors

  • Jürgen Teich
    • Computer EngineeringUniversity of Paderborn
  • Sándor P. Fekete
    • Department of Mathematics
  • Jörg Schepers
    • IBM Germany
Article

DOI: 10.1023/A:1011188411132

Cite this article as:
Teich, J., Fekete, S.P. & Schepers, J. The Journal of Supercomputing (2001) 19: 57. doi:10.1023/A:1011188411132

Abstract

Recent generations of Field Programmable Gate Arrays (FPGA) allow the dynamic reconfiguration of cells on the chip during run-time. For a given problem consisting of a set of tasks with computation requirements modeled by rectangles of cells, several optimization problems such as finding the array of minimal size to accomplish the tasks within a given time limit are considered. Existing approaches based on ILP formulations to solve these problems as multi-dimensional packing problems turn out not to be applicable for problem sizes of interest. Here, a breakthrough is achieved in solving these problems to optimality by using the new notion of packing classes. It allows a significant reduction of the search space such that problems of the above type may be solved exactly using a special branch-and-bound technique. We validate the usefulness of our method by providing computational results.

reconfigurable hardwaremulti-dimensional placement and packing

Copyright information

© Kluwer Academic Publishers 2001