Linear QR Architecture for a Single Chip Adaptive Beamformer
 G. Lightbody,
 R. Walke,
 R. Woods,
 J. McCanny
 … show all 4 hide
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This paper presents the design of a novel single chip adaptive beamformer capable of performing 50 Gflops, (Gigafloatingpoint operations/second). The core processor is a QR array implemented on a fully efficient linear systolic architecture, derived using a mapping that allows individual processors for boundary and internal cell operations. In addition, the paper highlights a number of rapid design techniques that have been used to realise this system. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilisation of a library of parameterisable silicon intellectual property (IP) cores, to rapidly develop detailed silicon designs.
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 Title
 Linear QR Architecture for a Single Chip Adaptive Beamformer
 Journal

Journal of VLSI signal processing systems for signal, image and video technology
Volume 24, Issue 1 , pp 6781
 Cover Date
 20000201
 DOI
 10.1023/A:1008118711904
 Print ISSN
 09225773
 Online ISSN
 1573109X
 Publisher
 Kluwer Academic Publishers
 Additional Links
 Topics
 Industry Sectors
 Authors

 G. Lightbody ^{(1)}
 R. Walke ^{(2)}
 R. Woods ^{(3)}
 J. McCanny ^{(1)}
 Author Affiliations

 1. DSiP™ Laboratories, Queen's University of Belfast, Belfast, N. Ireland
 2. DERA, St. Andrew's Road, Malvern, England
 3. Hardware Systems Group, Queen's University of Belfast, Belfast, N. Ireland