Journal of VLSI signal processing systems for signal, image and video technology

, Volume 24, Issue 1, pp 67-81

First online:

Linear QR Architecture for a Single Chip Adaptive Beamformer

  • G. LightbodyAffiliated withDSiP™ Laboratories, Queen's University of Belfast
  • , R. WalkeAffiliated withDERA
  • , R. WoodsAffiliated withHardware Systems Group, Queen's University of Belfast
  • , J. McCannyAffiliated withDSiP™ Laboratories, Queen's University of Belfast

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This paper presents the design of a novel single chip adaptive beamformer capable of performing 50 Gflops, (Giga-floating-point operations/second). The core processor is a QR array implemented on a fully efficient linear systolic architecture, derived using a mapping that allows individual processors for boundary and internal cell operations. In addition, the paper highlights a number of rapid design techniques that have been used to realise this system. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilisation of a library of parameterisable silicon intellectual property (IP) cores, to rapidly develop detailed silicon designs.