Abstract
Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip (SOC) test architecture. Prior research has concentrated on only one aspect of the TAM/wrapper design problem at a time, i.e., either optimizing the TAMs for a set of pre-designed wrappers, or optimizing the wrapper for a given TAM width. In this paper, we address a more general problem, that of carrying out TAM design and wrapper optimization in conjunction. We present an efficient algorithm to construct wrappers that reduce the testing time for cores. Our wrapper design algorithm improves on earlier approaches by also reducing the TAM width required to achieve these lower testing times. We present new mathematical models for TAM optimization that use the core testing time values calculated by our wrapper design algorithm. We further present a new enumerative method for TAM optimization that reduces execution time significantly when the number of TAMs being designed is small. Experimental results are presented for an academic SOC as well as an industrial SOC.
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References
J. Aerts and E.J. Marinissen, “Scan Chain Design for Test Time Reduction in Core-Based Ics,” in Proc. International Test Conference, 1998, pp. 448–457.
M. Berkelaar, lpsolve 3.0, Eindhoven University of Technology, Eindhoven, The Netherlands. ftp://ftp.ics.ele.tue.nl/pub/lp solve.
K. Chakrabarty, “Design of System-on-a-Chip Test Access Architectures Using Integer Linear Programming,” in Proc. VLSI Test Symposium, 2000, pp. 127–134.
K. Chakrabarty, “Design of System-on-a-Chip Test Access Architectures Under Place-and-Route and Power Constraints,” in Proc. Design Automation Conference, 2000, pp. 432–437.
K. Chakrabarty, “Optimal Test Access Architectures for Systemon-a-Chip,” ACM Transactions on Design Automation of Electronic Systems, vol. 6, pp. 26–49, Jan. 2001.
T.J. Chakraborty, S.6Bhawmik, and C-.H. Chiang, “Test Access Methodology for System-on-Chip Testing,” Digest of the International Workshop on Testing Embedded Core-Based System-Chips, 2000, pp. 1.1-1–1.1-7.
M.R. Garey and D.S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness, San Francisco, CA: W.H. Freeman and Co., 1979.
I. Ghosh, S. Dey, and N.K. Jha, “A Fast and Low Cost Testing Technique for Core-Based System-on-Chip,” in Proc. Design Automation Conference, 1998, pp. 542–547.
P. Harrod, “Testing Re-Usable IP: A Case Study,” in Proc. International Test Conference, 1999, pp. 493–498.
IEEE P1500 Standard for Embedded Core Test. http://grouper. ieee.org/groups/1500/.
V. Immaneni and S. Raman, “Direct Access Test Scheme— Design of Block and Core Cells for Embedded ASICs,” in Proc. International Test Conference, 1990, pp. 488–492.
E. Larsson and Z. Peng, “An Integrated System-on-Chip Test Framework,” in Proc. Design, Automation, and Test in Europe (DATE), 2001, pp. 138–144.
J.H. van Lint and R.M. Wilson, A Course in Combinatorics, Cambridge: Cambridge University Press, 1992.
E.J. Marinissen, R. Arendsen, G. Bos, H. Dingemanse, M. Lousbera, and C. Wouters, “A Structured and Scalable Mechanism for Test Access to Embedded Reusable Cores,” in Proc. International Test Conference, 1998, pp. 284–293.
E.J. Marinissen, S.K. Goel, and M. Lousberg, “Wrapper Design for Embedded Core Test,” in Proc. International Test Conference, 2000, pp. 911–920.
E.J. Marinissen, R. Kapur, and Y. Zorian, “On Using IEEE P1500 SECT for Test Plug-n-Play,” in Proc. International Test Conference, 2000, pp. 770–777.
M. Nourani and C. Papachristou, “An ILP Formulation to Optimize Test Access Mechanism in System-on-Chip Testing,” “IEEE International Test Conference, 2000, pp. 902–910.
Semiconductor Industry Association, International Technology Roadmap for Semiconductors, http://public.itrs.net/files/1999 SIA Roadmap/Home.htm.
N.A. Touba and B. Pouya, “Using Partial Isolation Rings to Test Core-Based Designs,” IEEE Design and Test of Computers, vol. 14, pp. 52–59, Oct.–Dec. 1997.
P. Varma and S. Bhatia, “A Structured Test Re-Use Methodology for Core-Based System Chips,” in Proc. International Test Conference, 1998, pp. 294–302. 230 Iyengar, Chakrabarty and Marinissen
H.P. Williams, Model Building in Mathematical Programming. 2nd ed., New York, NY: John Wiley, 1985.
Y. Zorian, E.J. Marinissen, and S. Dey, “Testing Embedded-Core-Based System Chips,” in Proc. International Test Conference, 1998, pp. 130–143.
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Iyengar, V., Chakrabarty, K. & Marinissen, E.J. Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip. Journal of Electronic Testing 18, 213–230 (2002). https://doi.org/10.1023/A:1014916913577
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DOI: https://doi.org/10.1023/A:1014916913577