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Reconfiguration-Based Defect-Tolerant Design Automation for Hybrid CMOS/Nanofabrics Circuits Using Evolutionary and Non-Deterministic Heuristics

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Abstract

Recently, a shift from CMOS lithography to nanoelectronics chemical assembly has been under investigation. Nanoscale components are assembled into arrays of low-power and high-density nanofabrics, which can be integrated with conventional CMOS systems. The inability to achieve inexpensive defect-free mass manufacturing of nanoelectronics is the largest impediment of their adoption. Limited nanowire lengths and defect-prone nanodevices pose significant challenges for design automation tools. In this work, we propose a design phase for cell mapping and reconfiguration in novel hybrid CMOS/nanoelectronics architecture called CMOL. Reconfiguration consists of finding new suitable physical location for each gate such that the circuit becomes defect free. The novelty of this work is to engineer non-deterministic iterative search heuristics, namely simulated evolution (SimE) and Tabu search (TS), to find cell assignment around defective nano-components. Circuits of various sizes from ISCAS’89 benchmarks are used to evaluate the designed heuristics. Results show that SimE and TS yield successful reconfigurations in reasonable computation time when nanodevice defect rate is as high as 50 % and nanowire cut rate up to 70 %.

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References

  1. Frank D.J., Dennard R.H., Nowak E., Solomon P.M., Taur Y., Philip Wong H.-S.: Device scaling limits of Si MOSFETs and their application dependencies. Proc. IEEE 89(3), 259–288 (2001)

    Article  Google Scholar 

  2. Konstantin, L.: Electronics below 10 nm. In: Greer, J.; Korkin, A.; Labanowski J. (eds.) Nano and Giga Challenges in Microelectronics, pp. 27–68. Elsevier, Amsterdam. http://dx.doi.org/10.1016/B978-044451494-3/50002-0 (2003)

  3. Park H., Park J., Lim A.K.L, Anderson E.H., Alivisatos A.P., McEuen P.L.: Nanomechanical oscillations in a single-C60 transistor. Nature 407(6800), 57–60 (2000)

    Article  Google Scholar 

  4. Kubatkin S., Danilov A., Hjort M., Cornil J., Bredas J.-L., Stuhr-Hansen N., Hedegard P., Bjornholm T.: Single-electron transistor of a single organic molecule with access to several redox states. Nature 425(6959), 698–701 (2003)

    Article  MATH  Google Scholar 

  5. Tougaw P.D., Lent C.S.: Logical devices implemented using quantum cellular automata. J. Appl. Phys. 75(3), 1818–1825 (1994)

    Article  Google Scholar 

  6. Collier C.P., Wong E.W., Belohradsky M., Raymo F.M., Stoddart J.F., Kuekes P.J., Williams R.S., Heath J.R.: Electronically configurable molecular-based logic gates. Science 285(5426), 391–394 (1999)

    Article  Google Scholar 

  7. Chen, J.; Reed, M.A.; Rawlett, A.M.; Tour, J.M.: Observation of a large on-off ratio and negative differential resistance in an electronic molecular switch. Science 286, 1550–1552 (1999)

  8. Zhirnov V.V., Herr D.J.C.: New frontiers: self-assembly and nanoelectronics. Computer 34(1), 34–43 (2001)

    Article  Google Scholar 

  9. Butts, M.; DeHon, A.: Molecular electronics: devices, systems and tools for Gigagate, Gigabit chips. In: In ICCAD-2002, pp. 433–440 (2002)

  10. Strukov D.B., Likharev K.K.: CMOL FPGA: a reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices. Nanotechnology 16(6), 888–900 (2005)

    Article  Google Scholar 

  11. Trel O., Lee J.H., Ma X., Likharev K.K.: Neuromorphic architectures for nanoelectronic circuits. Int. J. Circuit Theory Appl. 32(5), 277–302 (2004)

    Article  Google Scholar 

  12. Goldstein, S.C.; Budiu, M.: NanoFabrics: spatial computing using molecular electronics. In: 28th Annual International Symposium on Computer Architecture, 2001. Proceedings, pp. 178–189 (2001)

  13. DeHon, A.; Likharev, K.K.: Hybrid CMOS/nanoelectronic digital circuits: devices, architectures, and design automation. In: IEEE/ACM International Conference on Computer-Aided Design, 2005. ICCAD-2005, pp. 375–382 (2005)

  14. Snider G.S., Kuekes P.J., Williams R.S.: Crossbar nanocomputers. Sci. Am. 293(5), 72–76 (2005)

    Article  Google Scholar 

  15. Strukov, D.B.; Likharev, K.K.: CMOL FPGA circuits. In: In Proceedings of International Conference on Computer Design, CDES2006, pp. 213–219 (2006)

  16. Stan M.R., Franzon P.D., Goldstein S.C., Lach J.C., Ziegler M.M.: Molecular electronics: from devices and interconnect to circuits and architecture. Proc. IEEE 91(11), 1940–1957 (2003)

    Article  Google Scholar 

  17. Tahoori, M.B.; Mitra, S.: Fault detection and diagnosis techniques for molecular computing. In: In NanoTech (2004)

  18. Brown, J.G.; Blanton, R.D.: CAEN-BIST: testing the nanofabric. In: Test Conference, 2004. Proceedings. ITC 2004. International, pp. 462–471 (2004)

  19. Tehranipoor M., Rad R.M.P.: Built-in self-test and recovery procedures for molecular electronics-based nanofabrics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(5), 943–958 (2007)

    Article  Google Scholar 

  20. Joshi, M.V.; Al-Assadi, W.K.: A BIST approach for configurable nanofabric arrays. In: 8th IEEE Conference on Nanotechnology, 2008. NANO ’08. pp. 695–698 (2008)

  21. Sait, S.M.; Arafeh, A.M.: Cell assignment in hybrid CMOS/nanodevices architecture using Tabu Search. Appl. Intell. 40(1), 1–12 (2013)

  22. Strukov, D.B.; Likharev, K.K.: A reconfigurable architecture for hybrid CMOS/Nanodevice circuits. In: Proceedings of the 2006 ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA ’06, pp. 131–140, New York, NY, USA. ACM (2006)

  23. Hung W.N.N., Gao C., Song X., Hammerstrom D.: Defect-tolerant CMOL cell assignment via satisfiability. Sensors J. IEEE 8(6), 823–830 (2008)

    Article  Google Scholar 

  24. Xia, Y.; Chu, Z.; Hung, W.N.N.; Wang, L.; Song, X.: CMOL cell assignment by genetic algorithm. In: 2010 8th IEEE International NEWCAS Conference (NEWCAS), pp. 25–28 (2010)

  25. Chu, Z.; Xia, Y.; Hung, W.N.N.; Wang, L.; Song, X.: A memetic approach for nanoscale hybrid circuit cell mapping. In: 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD), pp. 681–688 (2010)

  26. Xia Y., Chu Z., Hung W., Wang L., Song X.: An integrated optimization approach for nano-hybrid circuit cell mapping. IEEE Trans. Nanotechnol. PP(99), 1 (2011)

    Google Scholar 

  27. Xu, C.; Nepal, K.: Ant-colony-optimization based heuristic searching algorithm for cell assignment in a hybrid cmos/nano circuits (cmol) array. In: 2014 IEEE 14th International Conference on Nanotechnology (IEEE-NANO), pp. 262–267 (2014)

  28. Sait, S.M.; Arafeh, A.M.: Efficient CMOL nanoscale hybrid circuit cell assignment using Simulated evolution heuristic. In: Proceedings of the great lakes symposium on VLSI, GLSVLSI ’12, pp. 21–26, New York, NY, USA. ACM (2012)

  29. Sait, S.M.; Arafeh, A.M.: Tabu Search based cells placement in nanofabric architectures with restricted connectivity. In: 2013 14th International Symposium on Quality Electronic Design (ISQED), pp. 487–493 (2013)

  30. Yellambalase Y., Choi M.: Cost-driven repair optimization of reconfigurable nanowire crossbar systems with clustered defects. J. Syst. Archit. 54(8), 729–741 (2008)

    Article  Google Scholar 

  31. Huang, J.; Tahoori, M.B.; Lombardi, F.: On the defect tolerance of nano-scale two-dimensional crossbars. In: 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings, pp. 96–104 (2004)

  32. Tahoori, M.B.: A mapping algorithm for defect-tolerance of reconfigurable nano-architectures. In: Proceedings of the 2005 IEEE/ACM International Conference on Computer-Aided Design, ICCAD ’05, pp. 668–672, Washington, DC, USA. IEEE Computer Society (2005)

  33. Arafeh, A.M.; Sait, S.M.: Cells reconfiguration around defects in CMOS/nanofabric circuits using Simulated Evolution heuristic. In: 2015 16th International Symposium on Quality Electronic Design (ISQED) (2015)

  34. Likharev D.B., Strukov K.K.: CMOL: devices, circuits, and architectures. Introd. Mol. Electron. Lect. Notes Phys. 680, 447–477 (2005)

    Article  Google Scholar 

  35. Sait S.M., Youssef H.: Iterative Computer Algorithms with Applications in Engineering: Solving Combinatorial Optimization Problems. IEEE Computer Society Press, California (1999)

    MATH  Google Scholar 

  36. Stapper C.H.: Simulation of spatial fault distributions for integrated circuit yield estimations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(12), 1314–1318 (1989)

    Article  Google Scholar 

  37. Stapper C.H.: Simulation of spatial fault distributions for integrated circuit yield estimations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(12), 1314–1318 (1989)

    Article  Google Scholar 

  38. Brglez, F.; Bryan, D.; Kozminski, K.: Combinational profiles of sequential benchmark circuits. In: IEEE International Symposium on Circuits and Systems, 1989, vol. 3, pp. 1929–1934 (1989)

  39. Sentovich, E.M.; Singh, K.J.; Lavagno, L.; Moon, C.; Murgai, R.; Saldanha, A.; Savoj, H.; Stephan, P.R.; Brayton, R.K.; Vincentelli, A.S.: SIS: a system for sequential circuit synthesis. Electronics Research Laboratory Memorandum, (UCB/ERL M92/41) (1992)

  40. Lee, H.K.; Ha, D.S.: HOPE: an efficient parallel fault simulator. In: Proceedings, 29th ACM/IEEE Design Automation Conference, 1992, pp. 336–340 (1992)

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Correspondence to Sadiq M. Sait.

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Abdalrahman M. Arafeh was at King Fahd University of Petroleum & Minerals when this work was done.

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Sait, S.M., Arafeh, A.M. Reconfiguration-Based Defect-Tolerant Design Automation for Hybrid CMOS/Nanofabrics Circuits Using Evolutionary and Non-Deterministic Heuristics. Arab J Sci Eng 40, 2515–2529 (2015). https://doi.org/10.1007/s13369-015-1682-1

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