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Explaining Engineered Computing Systems’ Behaviour: the Role of Abstraction and Idealization

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Abstract

This paper addresses the methodological problem of analysing what it is to explain observed behaviours of engineered computing systems (BECS), focusing on the crucial role that abstraction and idealization play in explanations of both correct and incorrect BECS. First, it is argued that an understanding of explanatory requests about observed miscomputations crucially involves reference to the rich background afforded by hierarchies of functional specifications. Second, many explanations concerning incorrect BECS are found to abstract away (and profitably so on account of both relevance and intelligibility of the explanans) from descriptions of physical components and processes of computing systems that one finds below the logic circuit and gate layer of functional specification hierarchies. Third, model-based explanations of both correct and incorrect BECS that are provided in the framework of formal verification methods often involve idealizations. Moreover, a distinction between restrictive and permissive idealizations is introduced and their roles in BECS explanations are analysed.

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Notes

  1. This neglect is at odds with a rising interest in methodological analyses of explanation in other areas of technological inquiry (see for instance Pitt 2011 and van Eck 2015).

  2. Floridi et al. (2014) distinguish between a dysfunction, an artefact’s behaviour not complying with user specifications, and a misfunction, an artefact’s behaviour which does comply with its specifications but is nevertheless prone to bring about undesired side effects. The authors emphasise how “the misfunction of an artifact token may be due to a dysfunction of some component” (p. 1209). Accordingly, explaining a misfunction of computing systems amounts to explaining a dysfunction of some given component of the system on the basis of the relevant specifications which ought to be fulfilled by such component.

  3. The shift amount field, named shamt and usually involved in data transfer and conditional-branch instructions, refers to the shift left side or right side of a given bit in an instruction. Here, it is set to 0, since it is of no significance for the \( slt \) instruction.

  4. In the taxonomy provided by Fresco and Primiero (2013), miscomputations engendered by wrongly conceived specifications are called mistakes.

  5. Syntax encoding errors count as slips in Fresco and Primiero’s (2013) terminology.

  6. In MIPS implementations, at each clock cycle of the processor, new data are written in all registers (whereas data can be read anytime).

  7. S-R latches do not take into consideration clock signals, so they are not, technically speaking, flip-flops. However, for the sake of simplicity, only S-R latches are considered here.

  8. This is an operational malfunction in Fresco and Primiero’s (2013) taxonomy.

  9. See (Trautteur and Tamburrini 2007, and especially pp. 107–108) for a discussion of the discrete-continuous polarity in the context of computing systems and their functional role fillers.

  10. The example is taken from Clarke et al. (1999, pp. 38–39).

  11. Kripke Structures have been more explicitly used to represent causal structures (see for instance Alur et al. 1998, p. 45). More in general, checking KSs against specified temporal formulas can be useful to infer causal relations from temporal data (Kleinberg 2012).

  12. Paths in the model violating the temporal logic formula are identifiable with counterexamples under the assumption that model M provides a correct representation of the reactive system for the specific verification purpose at hand. This crucial assumption can be empirically controlled by starting the reactive system under suitable initial conditions and verifying whether the runs that are actually observed are correctly modelled by those paths in the model which violate the temporal logic formula according to the model checking algorithm.

  13. A path is fair in case it satisfies each CTL fairness formula infinitely often, and a fair KS \( N=\left(S,\;{S}_0,\;R,\;L,\;F\right) \) is also defined by a set \( F\subseteq {2}^S \) of fairness constraints. A fairness constraint avoiding that unfair path be travelled by the model checking algorithm exploring the KS of Fig. 3 may be given by the formula \( Start\wedge Close\wedge \neg Error \) which, when satisfied by some fair path, requires that the system will eventually enter a non-error state. Considering a fair KS M° for the microwave oven, \( M{}^{\circ}{\models}_F\boldsymbol{A}\boldsymbol{G}\left( Start\to \boldsymbol{A}\boldsymbol{F}\; Heat\right) \), if there exists a fair path starting from an initial state, that is, witness π′′′= s0, s1, s5, s3, s6, s7.

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Acknowledgments

We are grateful to the anonymous reviewers who helped us to focus on the core theses of the paper and suggested valuable improvements.

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Angius, N., Tamburrini, G. Explaining Engineered Computing Systems’ Behaviour: the Role of Abstraction and Idealization. Philos. Technol. 30, 239–258 (2017). https://doi.org/10.1007/s13347-016-0235-1

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