Abstract
In this study, we investigate the effect of an etching process on the rectification property of a p-n junction. To achieve this goal, electrochemical etching (ECE) was employed, using a HF based solution. The morphological properties of the porous samples were characterized by Field Emission Scanning Electron Microscopy (FESEM). The images showed distributed pores in the range of several nanometers. Also, the distribution showed improvement in the size of meso- to macropores. The Current-Voltage measurement of porous and pristine poly silicon p-n junctions was done in dark and illumination conditions. I-V properties in illumination revealed intensive rectification in the proposed junction. Under dark condition, the ideality factor of the porous poly silicon p-n junction was approximately 3.9, which compared to 4.2 for the pristine sample demonstrates 7% improvement. Also, the light sensitivity was increased in the porous one. Furthermore, the light response (Δφ BP) of the porous sample gave the value of 0.02. In conclusion, the rectification mode could be enhanced through relevant porosity.
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Shiraz, H.G., Astaraei, F.R., Tavakoli, O. et al. The Effect of a Porous Layer on I-V Characterization of a Polysilicon p-n Junction. Silicon 10, 205–210 (2018). https://doi.org/10.1007/s12633-016-9417-9
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DOI: https://doi.org/10.1007/s12633-016-9417-9