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On the Way to Large-Scale and High-Resolution Brain-Chip Interfacing

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Abstract

Brain-chip-interfaces (BCHIs) are hybrid entities where chips and nerve cells establish a close physical interaction allowing the transfer of information in one or both directions. Typical examples are represented by multi-site-recording chips interfaced to cultured neurons, cultured/acute brain slices, or implanted “in vivo”. This paper provides an overview on recent achievements in our laboratory in the field of BCHIs leading to enhancement of signals transmission from nerve cells to chip or from chip to nerve cells with an emphasis on in vivo interfacing, either in terms of signal-to-noise ratio or of spatiotemporal resolution. Oxide-insulated chips featuring large-scale and high-resolution arrays of stimulation and recording elements are presented as a promising technology for high spatiotemporal resolution interfacing, as recently demonstrated by recordings obtained from hippocampal slices and brain cortex in implanted animals. Finally, we report on an automated tool for processing and analysis of acquired signals by BCHIs.

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Acknowledgments

This work was carried out as a part of the European Commission funded CyberRat project under the Seventh FrameworkProgramme (ICT-2007.8.3 Bio-ICT convergence, 216528, CyberRat). The authors express their gratitude to Prof. Peter Fromherz for providing us with the chips and his invaluable suggestions during the experiments & Prof. Roland Thewes for fruitful discussions and technical support.

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Authors and Affiliations

  1. NeuroChip Laboratory, Department of Human Anatomy and Physiology, University of Padova, 35131, Padua, Italy

    Stefano Vassanelli, Mufti Mahmud, Stefano Girardi & Marta Maschietto

  2. Institute of Information Technology, Jahangirnagar University, Savar, 1342, Dhaka, Bangladesh

    Mufti Mahmud

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  1. Stefano Vassanelli
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  2. Mufti Mahmud
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Correspondence to Stefano Vassanelli.

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Vassanelli, S., Mahmud, M., Girardi, S. et al. On the Way to Large-Scale and High-Resolution Brain-Chip Interfacing. Cogn Comput 4, 71–81 (2012). https://doi.org/10.1007/s12559-011-9121-4

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  • DOI: https://doi.org/10.1007/s12559-011-9121-4

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