Abstract
Image and video processing applications represent major challenge concerning real-time embedded systems. In video coding, adjacent frames are similar; this correlation can be exploited to reduce the amount of data to be transmitted, in this case reducing temporal redundancies. Actually, H.264/AVC is the most popular standard; the high performance that offers magnifies the difficulty of a real-time implementation. This complexity is mainly related to the operation of the motion estimation and requires high computational power. This paper presents an efficient hardware implementation of integer motion estimation for H.264/AVC encoder. The considered methodology is based on full search block matching algorithm for its regular algorithm implementation. The proposed architecture enables variable block size motion estimation and computes 41 motion vectors values (MVs) resulted from each 16 × 16 bloc and its derived sub-blocks. The proposed architecture calculates the best MV using a parallel process composed of three processor modules and a set of comparators three values. Implementation results based on field-programmable gate arrays devices uses Xilinx Virtex7 XC7VX550T show performance characteristics like low latency reduced up to 80 %, high processing speed reaching 443 MHz of frequency. The processing capacity is up to 1920 × 1088 HD video streams with a search range of 48 × 48.
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Yahi, A., Toumi, S., Bourennane, Eb. et al. A speed FPGA hardware accelerator based FSBMA-VBSME used in H.264/AVC. Evolving Systems 7, 233–241 (2016). https://doi.org/10.1007/s12530-015-9140-6
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DOI: https://doi.org/10.1007/s12530-015-9140-6