Skip to main content
SpringerLink
Log in

Optimized stateful material implication logic for three-dimensional data manipulation

  • Research Article
  • Published:
Nano Research Aims and scope Submit manuscript

Abstract

The monolithic three-dimensional integration of memory and logic circuits could dramatically improve the performance and energy efficiency of computing systems. Some conventional and emerging memories are suitable for vertical integration, including highly scalable metal-oxide resistive switching devices (“memristors”). However, the integration of logic circuits has proven to be much more challenging than expected. In this study, we demonstrated memory and logic functionality in a monolithic three-dimensional circuit by adapting the recently proposed memristor-based stateful material implication logic. By modifying the original circuit to increase its robustness to device imperfections, we experimentally showed, for the first time, a reliable multi-cycle multi-gate material implication logic operation and half-adder circuit within a threedimensional stack of monolithically integrated memristors. Direct data manipulation in three dimensions enables extremely compact and high-throughput logicin- memory computing and, remarkably, presents a viable solution for the Feynman Grand Challenge of implementing an 8-bit adder at the nanoscale.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. Borghetti, J.; Snider, G. S.; Kuekes, P. J.; Yang, J. J.; Stewart, D. R.; Williams, R. S. “Memristive” switches enable “stateful” logic operations via material implication. Nature 2010, 464, 873–876.

    Article  Google Scholar 

  2. Yang, J. J.; Strukov, D. B.; Stewart, D. R. Memristive devices for computing. Nat. Nanotechnol. 2013, 8, 13–24.

    Article  Google Scholar 

  3. Wong, H.-S. P.; Salahuddin, S. Memory leads the way to better computing. Nat. Nanotechnol. 2015, 10, 191–194.

    Article  Google Scholar 

  4. Chevallier, C. J.; Siau, C. H.; Lim, S. F.; Namala, S. R.; Matsuoka, M.; Bateman, B. L.; Rinerson, D. A 0.13 µm 64 Mb multi-layered conductive metal-oxide memory. In Proceedings of the 2010 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, USA, 2010, pp 260–261.

    Chapter  Google Scholar 

  5. Kawahara, A.; Azuma, R.; Ikeda, Y.; Kawai, K.; Katoh, Y.; Hayakawa, Y.; Tsuji, K.; Yoneda, S.; Himeno, A.; Shimakawa, K. et al. An 8 Mb multi-layered cross-point ReRAM macro with 443 MB/s write throughput. IEEE J Solid-State Circuits 2013, 48, 178–185.

    Article  Google Scholar 

  6. Yu, S. M.; Chen, H.-Y.; Gao, B.; Kang, J. F.; Wong, H.-S. P. HfOx-based vertical resistive switching random access memory suitable for bit-cost-effective three-dimensional cross-point architecture. ACS Nano 2013, 7, 2320–2325.

    Article  Google Scholar 

  7. Liu, T. Y.; Yan, T. H.; Scheuerlein, R.; Chen, Y. C.; Lee, J. K. Y.; Balakrishnan, G.; Yee, G.; Zhang, H.; Yap, A.; Ouyang, J. W. et al. A 130.7-mm2-layer 32-Gb ReRAM memory device in 24-nm technology. IEEE J. Solid-State Circuits 2014, 49, 140–153.

    Article  Google Scholar 

  8. Govoreanu, B.; Redolfi, A.; Zhang, L.; Adelmann, C.; Popovici, M.; Clima, S.; Hody, H.; Paraschiv, V.; Radu, I. P.; Franquet, A. et al. Vacancy-modulated conductive oxide resistive RAM (VMCO-RRAM): An area-scalable switching current, self-compliant, highly nonlinear and wide on/offwindow resistive switching cell. In Proceedings of the 2013 IEEE International Electron Devices Meeting (IEDM), Washington DC, USA, 2013.

    Google Scholar 

  9. Likharev, K. K.; Korotkov, A. N. “Single-electron parametron”: Reversible computation in a discrete state system. Science 1996, 273, 763–765.

    Article  Google Scholar 

  10. Cowburn, R. P.; Welland, M. E. Room temperature magnetic quantum cellular automata. Science 2000, 287, 1466–1468.

    Article  Google Scholar 

  11. Behin-Aein, B.; Datta, D.; Salahuddin, S.; Datta, S. Proposal for an all-spin logic device with built-in memory. Nat. Nanotechnol. 2010, 5, 266–270.

    Article  Google Scholar 

  12. Di Ventra, M.; Pershin, Y. V. The parallel approach. Nat. Phys. 2013, 9, 200–202.

    Article  Google Scholar 

  13. Chang, M. F.; Yang, S.-M.; Kuo, C.-C.; Yang, T.-C.; Yeh, C-J.; Chien, T.-F.; Huang, L.-Y.; Sheu, S.-S.; Tseng, P.-L.; Chen, Y.-S. et al. Set-triggered-parallel-reset memristor logic for high-density heterogeneous-integration friendly normally off applications. IEEE Trans. Circuits Syst. II, Exp. Briefs 2015, 62, 80–84.

    Article  Google Scholar 

  14. Wulf, W. A.; McKee, S. A. Hitting the memory wall: Implications of the obvious. ACM/SIGARCH Computer Architecture News 1995, 23, 20–24.

    Article  Google Scholar 

  15. Shin, S.; Kim, K.; Kang, S. M. Resistive computing: Memristors-enabled signal multiplication. IEEE Trans. Circuits Syst. I, Reg. Papers 2013, 60, 1241–1249.

    Article  Google Scholar 

  16. Zhu, X.; Yang, X. J.; Wu, C. Q.; Xiao, N.; Wu, J. J.; Yi, X. Performing stateful logic on memristor memory. IEEE Trans. Circuits Syst. II, Exp. Briefs 2013, 60, 682–686.

    Article  Google Scholar 

  17. Levy, Y.; Bruck, J.; Cassuto, Y.; Friedman, E. G.; Kolodny, A.; Yaakobi, E.; Kvatinsky, S. Logic operations in memory using a memristive Akers array. Microelectron. J. 2014, 45, 1429–1437.

    Article  Google Scholar 

  18. Mane, P.; Talati, N.; Riswadkar, A.; Raghu, R.; Ramesha, C. K. Stateful-NOR based reconfigurable architecture for logic implementation. Microelectron. J. 2015, 46, 551–562.

    Article  Google Scholar 

  19. Hamdioui, S.; Xie, L.; Nguyen, H. A. D.; Taouil, M.; Bertels, K.; Corporaal, H.; Jiao, H. L.; Catthoor, F.; Wouters, D.; Eike, L. et al. Memristor based computation-in-memory architecture for data-intensive applications. In Proceedings of Design, Automation and Test in Europe Conference & Exhibition (DATE), Grenoble, France, 2015, pp 1718–1725.

    Google Scholar 

  20. Lehtonen, E.; Poikonen, J. H.; Tissari, J.; Laiho, M.; Koskinen, L. Recursive algorithms in memristive logic arrays. IEEE Trans. Emerg. Sel. Topics Circuits Syst. 2015, 5, 279–292.

    Article  Google Scholar 

  21. Xie, L.; Nguyen, H. A. D.; Taouil, M.; Bertels, K.; Hamdioui, S. Fast boolean logic mapped on memristor crossbar. In Proceedings of the 2015 33rd International Conference on Computer Design (ICCD), New York City, USA, 2015, pp 335–342.

    Google Scholar 

  22. Li, H.; Gao, B.; Chen, Z.; Zhao, Y.; Huang, P.; Ye, H.; Liu, L.; Liu, X.; Kang, J. A learnable parallel processing architecture towards unity of memory and computing. Sci. Rep. 2015, 5, 13330.

    Article  Google Scholar 

  23. Sun, X. W.; Li, G. Q.; Ding, L. H.; Yang, N.; Zhang, W. F. Unipolar memristors enable “stateful” logic operations via material implication. Appl. Phys. Lett. 2011, 99, 072101.

    Article  Google Scholar 

  24. Prezioso, M.; Riminucci, A.; Graziosi, P.; Bergenti, I.; Rakshit, R.; Cecchini, R.; Vianelli, A.; Borgatti, F.; Haag, N.; Willis, M. et al. A single-device universal logic gate based on a magnetically enhanced memristor. Adv. Mater. 2013, 25, 534–538.

    Google Scholar 

  25. Elstner, M.; Weisshart, K.; Mü llen, K.; Schiller, A. Molecular logic with a saccharide probe on the few-molecules level. J. Am. Chem. Soc. 2012, 134, 8098–8100.

    Article  Google Scholar 

  26. Mahmoudi, H.; Windbacher, T.; Sverdlov, V.; Selberherr, S. Implication logic gates using spin-transfer-torque-operated magnetic tunnel junctions for intrinsic logic-in-memory. Solid-State Electron. 2013, 84, 191–197.

    Article  Google Scholar 

  27. Siemon, A.; Breuer, T.; Aslam, N.; Ferch, S.; Kim, W.; van den Hurk, J.; Rana, V.; Hoffmann-Eifert, S.; Waser, R.; Menzel, S. et al. Realization of Boolean logic functionality using redox-based memristive devices. Adv. Funct. Mat. 2015, 25, 6414–6423.

    Article  Google Scholar 

  28. Balatti, S.; Ambrogio, S.; Ielmini, D. Normally-off logic based on resistive switches - part II: Logic circuits. IEEE Trans. Electron Devices 2015, 62, 1839–1847.

    Article  Google Scholar 

  29. Zhou, Y. X.; Li, Y.; Xu, L.; Zhong, S. J.; Xu, R. G.; Miao, X. S. A hybrid memristor-CMOS XOR gate for nonvolatile logic computation. Phys. Status Solidi A 2016, 213, 1050–1054.

    Article  Google Scholar 

  30. Kvatinsky, S.; Satat, G.; Wald, N.; Friedman, E. G.; Kolodny, A.; Weiser, U. C. Memristor-based material implication (IMPLY) logic: Design principles and methodologies. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2014, 22, 2054–2066.

    Article  Google Scholar 

  31. Lehtonen, E.; Poikonen, J. H.; Laiho, M. Applications and limitations of memristive implication logic. In Proceedings of the 2012 13th International Workshop on Cellular Nanoscale Networks and their Applications (CNNA), Turin, Italy, 2012.

    Google Scholar 

  32. Siemon, A.; Menzel, S.; Chattopadhyay, A.; Waser, R.; Linn, E. In-memory adder functionality in 1S1R arrays. In Proceedings of the 2015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, 2015, pp 1338–1341.

    Chapter  Google Scholar 

  33. Ferch, S.; Linn, E.; Waser, R.; Menzel, S. Simulation and comparison of two sequential logic-in-memory approaches using a dynamic electrochemical metallization cell model. Microelectron. J. 2014, 45, 1416–1428.

    Article  Google Scholar 

  34. Kim, K.; Shin, S.; Kang, S. M. Field programmable stateful logic array. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. 2011, 30, 1800–1813.

    Article  Google Scholar 

  35. Topol, A. W.; La Tulipe, D. C.; Shi, L.; Frank, D. J.; Bernstein, K.; Steen, S. E.; Kumar, A.; Singco, G. U.; Young, A. M.; Guarini, K. W. et al. Three-dimensional integrated circuits. IBM J. Res. Develop. 2006, 50, 491–506.

    Article  Google Scholar 

  36. Xie, Y.; Loh, G. H.; Black, B.; Bernstein, K. Design space exploration for 3D architectures. ACM JETC 2006, 2, 65–103.

    Article  Google Scholar 

  37. Lehtonen, E.; Poikonen, J. H.; Laiho, M. Memristive Stateful Logic. In Memristor Networks; Adamatzky, A.; Chua, L., Eds.; Springer International Publishing: Switzerland, 2014; pp 603–623.

    Chapter  Google Scholar 

  38. Prezioso, M.; Merrikh-Bayat, F.; Hoskins, B. D.; Adam, G. C.; Likharev, K. K.; Strukov, D. B. Training and operation of an integrated neuromorphic network based on metal-oxide memristors. Nature 2015, 521, 61–64.

    Article  Google Scholar 

  39. Yang, J. J.; Pickett, M. D.; Li, X. M.; Ohlberg, D. A. A.; Stewart, D. R.; Williams, R. S. Memristive switching mechanism for metal/oxide/metal nanodevices. Nat. Nanotechnol. 2008, 3, 429–433.

    Article  Google Scholar 

  40. Mikheev, E.; Hoskins, B. D.; Strukov, D. B.; Stemmer, S. Resistive switching and its suppression in Pt/Nb: SrTiO3 junctions. Nat. Commun. 2014, 5, 3990.

    Article  Google Scholar 

  41. Sun, P. X.; Lu, N. D.; Li, L.; Li, Y. T.; Wang, H.; Lv, H. B.; Liu, Q.; Long, S. B.; Liu, S.; Liu, M. Thermal crosstalk in 3-dimensional RRAM crossbar array. Sci. Rep. 2015, 5, 13504.

    Article  Google Scholar 

  42. Prezioso, M.; Kataeva, I.; Merrikh-Bayat, F.; Hoskins, B.; Adam, G.; Sota, T.; Likharev, K.; Strukov, D. Modeling and implementation of firing-rate neuromorphic-network classifiers with bilayer Pt/Al2O3/TiO2–x /Pt Memristors. In Proceedings of the 2015 IEEE International Electron Devices Meeting (IEDM), Washington DC, USA, 2015.

    Google Scholar 

  43. Feynman Grand Prize [Online]. https://www.foresight.org/GrandPrize.1.html (accessed May 5, 2016).

  44. Yang, J. J.; Miao, F.; Pickett, M. D.; Ohlberg, D. A. A.; Stewart, D. R.; Lau, C. N.; Williams, R. S. The mechanism of electroforming of metal oxide memristive switches. Nanotechnology 2009, 20, 215201.

    Article  Google Scholar 

  45. Varesi, J.; Majumdar, A. Scanning Joule expansion microscopy at nanometer scales. Appl. Phys. Lett. 1998, 72, 37–39.

    Article  Google Scholar 

  46. Parhami, B. Computer Arithmetic: Algorithms and Hardware Designs; Oxford University Press: New York, NY, 2009.

    Google Scholar 

  47. Pi, S.; Lin, P.; Xia, Q. F. Cross point arrays of 8 nm × 8 nm memristive devices fabricated with nanoimprint lithography. J. Vac. Sci. Technol. B 2013, 31, 06FA02.

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Electrical and Computer Engineering Department, University of California Santa Barbara, Santa Barbara, CA, 93106, USA

    Gina C. Adam, Mirko Prezioso & Dmitri B. Strukov

  2. Materials Department, University of California Santa Barbara, Santa Barbara, CA, 93106, USA

    Brian D. Hoskins

Authors
  1. Gina C. Adam
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Brian D. Hoskins
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Mirko Prezioso
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Dmitri B. Strukov
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding authors

Correspondence to Gina C. Adam or Dmitri B. Strukov.

Electronic supplementary material

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Adam, G.C., Hoskins, B.D., Prezioso, M. et al. Optimized stateful material implication logic for three-dimensional data manipulation. Nano Res. 9, 3914–3923 (2016). https://doi.org/10.1007/s12274-016-1260-1

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s12274-016-1260-1

Keywords

Search

Navigation